On Fri, Nov 29, 2013 at 03:44:31PM +0530, deepak.s@xxxxxxxxx wrote: > From: Deepak S <deepak.s@xxxxxxxxx> > > On VLV, FIFO will be shared by both SW and HW. So, we read the > free entries through register and update dev_priv variable > and wait for only 20 entries to be free But the whole point of leaving 20 entries is for hardware has a portion of the fifo it can use for its own nefarious deeds. The hw has been emitting mmio through the write fifo since its inception on gen6, so what is so different for vlv? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
