On Wed, 27 Nov 2013 21:14:03 +0530 deepak.s@xxxxxxxxx wrote: > From: Deepak S <deepak.s@xxxxxxxxx> > > For RC6 Timeout method, we need to set promotion timer to 1750 us ( 1367 > * 1.28 us) > > Signed-off-by: Deepak S <deepak.s@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 04e9863..cf3d54d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4102,7 +4102,8 @@ static void valleyview_enable_rps(struct drm_device *dev) > for_each_ring(ring, dev_priv, i) > I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); > > - I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350); > + /* Timer for RC6 Timeout Mode set to 1750 us ( 1367 * 1.28 us) */ > + I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); > > /* allows RC6 residency counter to work */ > I915_WRITE(VLV_COUNTER_CONTROL, Yeah I just sent this one too. I'm fine with either one getting in. I also submitted one to do parallel restore of ring state, which we also want. Care to review my earlier ones? http://lists.freedesktop.org/archives/intel-gfx/2013-November/036112.html http://lists.freedesktop.org/archives/intel-gfx/2013-November/036111.html Thanks, -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
