From: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
These registers are currently used by mesa for blitting and
for transform feedback extensions.
Signed-off-by: Brad Volkin <bradley.d.volkin@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 33 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 8ee4cda..1decff9 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -140,6 +140,34 @@ static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
{ blt_cmds, ARRAY_SIZE(blt_cmds) },
};
+/* Register whitelists, sorted by increasing register offset.
+ *
+ * Some registers that userspace accesses are 64 bits. The register
+ * access commands only allow 32-bit accesses. Hence, we have to include
+ * entries for both halves of the 64-bit registers.
+ */
+
+static const u32 gen7_render_regs[] = {
+ CL_INVOCATION_COUNT,
+ CL_INVOCATION_COUNT + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(0),
+ GEN7_SO_NUM_PRIMS_WRITTEN(0) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(1),
+ GEN7_SO_NUM_PRIMS_WRITTEN(1) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(2),
+ GEN7_SO_NUM_PRIMS_WRITTEN(2) + sizeof(u32),
+ GEN7_SO_NUM_PRIMS_WRITTEN(3),
+ GEN7_SO_NUM_PRIMS_WRITTEN(3) + sizeof(u32),
+ GEN7_SO_WRITE_OFFSET(0),
+ GEN7_SO_WRITE_OFFSET(1),
+ GEN7_SO_WRITE_OFFSET(2),
+ GEN7_SO_WRITE_OFFSET(3),
+};
+
+static const u32 gen7_blt_regs[] = {
+ BCS_SWCTRL,
+};
+
#define CLIENT_MASK 0xE0000000
#define SUBCLIENT_MASK 0x18000000
#define MI_CLIENT 0x00000000
@@ -212,6 +240,9 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
+ ring->reg_table = gen7_render_regs;
+ ring->reg_count = ARRAY_SIZE(gen7_render_regs);
+
ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
break;
case VCS:
@@ -222,6 +253,8 @@ void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
case BCS:
ring->cmd_tables = gen7_blt_cmds;
ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
+ ring->reg_table = gen7_blt_regs;
+ ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
break;
case VECS:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d52569..aa43624 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -371,6 +371,15 @@
#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
/*
+ * Registers used only by the command parser
+ */
+#define BCS_SWCTRL 0x22200
+
+#define CL_INVOCATION_COUNT 0x2338
+/* There are the 4 64-bit counter registers, one for each stream output */
+#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
+
+/*
* Reset registers
*/
#define DEBUG_RESET_I830 0x6070
--
1.8.4.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
