On Mon, Nov 25, 2013 at 09:54:33AM -0800, Ben Widawsky wrote:
> The initial implementation of this function used MMIO to write the PDPs.
> Upon review it was determined (correctly) that the docs say to use LRI.
> The issue is there are times where we want to do a synchronous write
> (GPU reset).
>
> I've tested this, and it works. I've verified with as many people as
> possible that it should work.
>
> This should fix the failing reset problems.
>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1a5272c..96dbf3d 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -197,12 +197,19 @@ static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
>
> /* Broadwell Page Directory Pointer Descriptors */
> static int gen8_write_pdp(struct intel_ring_buffer *ring, unsigned entry,
> - uint64_t val)
> + uint64_t val, bool synchronous)
> {
> + struct drm_i915_private *dev_priv = ring->dev->dev_private;
> int ret;
>
i915_reset_in_progress(&dev_priv->gpu_error));
doesn't actually mean that we are in the middle of a reset. Or does
it? Anyway intel_ring_begin() returns EIO/EAGAIN so we do not need
to pass down the parameter. But the issue with mixing and matching LRI
vs mmio is that if this was not a reset call, then we just upset the
GPU even further.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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