On Thu, Nov 21, 2013 at 11:22:14PM +0000, Chris Wilson wrote: > On Thu, Nov 21, 2013 at 09:29:45PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > SNB has another register where the actual FBC CPU fence number is > > stored. The documenation explicitly states that the fence number > > in DPFC_CTL must be 0 on SNB. And in fact when it's not zero, > > the GTT tracking simply doesn't work. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
