PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
wake-up scanline counting starts from vblank_start - 1. We don't know if
wake-up is already ongoing when evasion starts. In worst case PIPEDSL could
start reading valid value right after checking the scanline. In this
scenario we wouldn't have enough time to write all registers. To tackle
this evade scanline 0 as well. As a drawback we have 1 frame delay in flip
when waking up.
v2:
- use intel_dsb_emit_wait_dsl
- add evasion of scanline 0 also for Panel Replay
Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 30782ab0b9082..f15e6c2a195c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -538,6 +538,18 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state,
int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20);
int start, end;
+ /*
+ * PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On
+ * wake-up scanline counting starts from vblank_start - 1. We don't know
+ * if wake-up is already ongoing when evasion starts. In worst case
+ * PIPEDSL could start reading valid value right after checking the
+ * scanline. In this scenario we wouldn't have enough time to write all
+ * registers. To tackle this evade scanline 0 as well. As a drawback we
+ * have 1 frame delay in flip when waking up.
+ */
+ if (crtc_state->has_psr)
+ intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0);
+
if (pre_commit_is_vrr_active(state, crtc)) {
int vblank_delay = intel_vrr_vblank_delay(crtc_state);
--
2.43.0
