From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
The FBC RT address is stored in the context, and thus needs to be
rewritten after a context switch before any batches are run. We emit
the LRI to update the FBC RT address when we call the ring ->flush
function to invalidate the caches.
When a context switch is being performed we currently do the
invalidate before the context switch, which means we're not updating
the FBC RT address correctly. Move the i915_gem_execbuffer_move_to_gpu()
call to happen after i915_switch_context() to make the LRI happen
after the MI_SET_CONTEXT.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 2d96edf..7389e7a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1181,10 +1181,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
i915_gem_execbuffer_mark_fbc_dirty(ring, &eb->vmas);
- ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
- if (ret)
- goto err;
-
hs = i915_gem_context_get_hang_stats(dev, file, ctx_id);
if (IS_ERR(hs)) {
ret = PTR_ERR(hs);
@@ -1200,6 +1196,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (ret)
goto err;
+ ret = i915_gem_execbuffer_move_to_gpu(ring, &eb->vmas);
+ if (ret)
+ goto err;
+
if (ring == &dev_priv->ring[RCS] &&
mode != dev_priv->relative_constants_mode) {
ret = intel_ring_begin(ring, 4);
--
1.8.3.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
