On Wed, Nov 20, 2013 at 12:47 PM, Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> wrote: > FAIL WaDisableEarlyCull:ivb > OK WaDisableBackToBackFlipFix:ivb > FAIL WaDisablePSDDualDispatchEnable:ivb > FAIL WaDisableRHWOptimizationForRenderHang:ivb > FAIL WaApplyL3ControlAndL3ChickenMode:ivb > OK WaForceL3Serialization:ivb > OK WaDisableRCZUnitClockGating:ivb > OK WaCatErrorRejectionIssue:ivb > FAIL WaVSRefCountFullforceMissDisable:ivb > FAIL WaDisable4x2SubspanOptimization:ivb Looks like just a bunch of render related registers, so could make sense to move them. I guess the bigger question is what happens if we use per-ring reset. Do we loose all the same register settings as for a full reset or is there some fancy split? Can you please check this out with your per-ring reset patches if possible? Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
