On Thu, Oct 31, 2013 at 09:53:36AM +0100, Daniel Vetter wrote: > Now we have this everywhere. Next up would be to wire up the DP > hotplug pin to speed up panel power sequencing for eDP panels ... > > I've decided to leave the has_aux_irq logic in the code, it should > come handy for hw bringup. > > For testing/fail-safety the dp aux code already has a timeout when > waiting for interrupts to signal completion and screams rather loud if > they don't arrive in time. Given that we need a real piece of hw to > talk to anyway this is probably as good as it gets. > > v2: Don't check the dp aux channel bits on i965 machines, they have a > different meaning there. Yay for reusing bits at will! Spotted by > Jani. > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx> Oops, I've seemed to have missed this one here. Merged to dinq. -Daniel > --- > drivers/gpu/drm/i915/i915_irq.c | 7 +++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_dp.c | 2 +- > 3 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 2a44816..a2bfcdb 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1375,6 +1375,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg) > > intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); > > + if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) > + dp_aux_irq_handler(dev); > + > I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > I915_READ(PORT_HOTPLUG_STAT); > } > @@ -3256,6 +3259,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > intel_hpd_irq_handler(dev, hotplug_trigger, > IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); > > + if (IS_G4X(dev) && > + (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) > + dp_aux_irq_handler(dev); > + > I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > I915_READ(PORT_HOTPLUG_STAT); > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 4d2db59..447fd83 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2116,6 +2116,10 @@ > #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) > #define CRT_HOTPLUG_MONITOR_MONO (2 << 8) > #define CRT_HOTPLUG_MONITOR_NONE (0 << 8) > +#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) > +#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) > +#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) > +#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (1 << 4) > /* SDVO is different across gen3/4 */ > #define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) > #define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index b3cc333..7fa4518 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > int i, ret, recv_bytes; > uint32_t status; > int try, precharge, clock = 0; > - bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); > + bool has_aux_irq = true; > > /* dp aux is extremely sensitive to irq latency, hence request the > * lowest possible wakeup latency and so prevent the cpu from going into > -- > 1.8.4.rc3 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
