On Sat, Nov 16, 2013 at 9:57 PM, Thomas Richter <thor@xxxxxxxxxxxxxxxxx> wrote: > Hi Daniel, dear intel experts, > > as reported yesterday, the watermark levels - the values of the FW_BLC > register are completely off on my R31. This renders the display unusable > after Daniel's patch from Friday, both the internal and the external. The > fwater_lo values for planes A and B need to be *at least* 6, while the > current algorithm sets them to one. Thus, the display flickers (now > constantly) because the watermark values are wrong. > > I now checked the code in intel_pm.c and I wonder how that actually works. > The display becomes in my experiments *more stable* if I increase the > watermark register value (i.e. FW_BLC), thus higher values refer to a higher > watermark, i.e. the chipset starts fetching data earlier. So far my > observation. > > However, the way how intel_calculate_wm is written, it subtracts the number > of necessary entries from the fifo size, and thus is written under the > assumption that the FIFO drains in the direction of increasing entries. > Thus, for the model used in intel_calculate_wm, *higher values* indicate a > *lower watermark*, i.e. would instruct the > DMA engine to fetch data later. > > This is in contradiction to my observation where higher values indicate > an *earlier* (and not a later) fetch. > > Thus, is the definition of the FW_BLC register possibly simply wrong? Or is > the subtraction in intel_calculate_wm possibly wrong? First: Have you tried my little patch, since the current watermark code for i830M is clearly completely busted? Otherwise the spec is fairly clear that lower values means to fetch earlier. One issue though is that atm we hardcode the burst-lenght to 0x3, which means 8*32 bytes. If the watermark is lower than 8*32 then the spec says that hilarity will ensue. I'll wip up a quick patch to add some #defines to i915_reg.h and use them in the code for better documentation. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
