On Mon, Nov 11, 2013 at 02:46:28PM -0800, Ben Widawsky wrote:
> The pipe B and pipe C interrupt mask and enable registers are now part
> of the pipe, so disabling the pipe power wells will lost the contests of
> the registers.
>
> Art totally debugged this one!
>
> v2: Use the irq_lock to clarify code, and prevent future bugs (Daniel)
>
> Cc: Art Runyan <arthur.j.runyan@xxxxxxxxx>
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
Merged to bdw-fixes, thanks.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0a07d7c..38915dc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5684,6 +5684,7 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> bool is_enabled, enable_requested;
> + unsigned long irqflags;
> uint32_t tmp;
>
> tmp = I915_READ(HSW_PWR_WELL_DRIVER);
> @@ -5701,9 +5702,22 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
> HSW_PWR_WELL_STATE_ENABLED), 20))
> DRM_ERROR("Timeout enabling power well\n");
> }
> +
> + if (IS_BROADWELL(dev)) {
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> + I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
> + dev_priv->de_irq_mask[PIPE_B]);
> + I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
> + ~dev_priv->de_irq_mask[PIPE_B] | GEN8_PIPE_VBLANK);
> + I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
> + dev_priv->de_irq_mask[PIPE_C]);
> + I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
> + ~dev_priv->de_irq_mask[PIPE_C] | GEN8_PIPE_VBLANK);
> + POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> + }
> } else {
> if (enable_requested) {
> - unsigned long irqflags;
> enum pipe p;
>
> I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
> --
> 1.8.4.2
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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