On Mon, Nov 11, 2013 at 11:12:57AM +0200, Jani Nikula wrote: > From: Ben Widawsky <benjamin.widawsky@xxxxxxxxx> > > Prior to Haswell the CPU control register for backlight > (BLC_PWM_CPU_CTL) toggled the PCH baclight pin for us. This made some > sense as there was no pin on the CPU. With Haswell came the introduction > of a CPU backlight pin, but the interface was still controlled by > software with the same mechnism. Behind the scenes, hardware did all the > dirty work for us. > > Broadwell no longer provides this for free. If we want to use the PCH > backlight pin [1] then we have to set the override bit BLC_PWM_PCH_CTL1 > and program BLC_PWM_PCH_CTL2 for the PWM values. > > This patch implements that. This patch is compile tested only, and given > that I rarely if ever touch this code, careful review is welcome. > > [1] According to Art, we know of no devices that exist which use the CPU > pin (and remember it has existed already on HSW). If such a device does > exist, we'll have to handle it properly - this is left as TODO until > then. > > v2: Drop the abstraction prep patch, as a bigger backlight overhaul is > in the works, and do just the mimimal bdw enabling now. (by Jani) > > CC: Art Runyan <arthur.j.runyan@xxxxxxxxx> > Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx> > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> Merged to bdw-fixes, thanks. -Daniel > > --- > > This supersedes: > http://mid.gmane.org/1383889251-498-14-git-send-email-benjamin.widawsky@xxxxxxxxx > http://mid.gmane.org/1383889251-498-15-git-send-email-benjamin.widawsky@xxxxxxxxx > --- > drivers/gpu/drm/i915/intel_panel.c | 26 +++++++++++++++++++++++--- > 1 file changed, 23 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index f161ac0..e6f782d 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -451,7 +451,9 @@ static u32 intel_panel_get_backlight(struct drm_device *dev, > > spin_lock_irqsave(&dev_priv->backlight.lock, flags); > > - if (HAS_PCH_SPLIT(dev)) { > + if (IS_BROADWELL(dev)) { > + val = I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; > + } else if (HAS_PCH_SPLIT(dev)) { > val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; > } else { > if (IS_VALLEYVIEW(dev)) > @@ -479,6 +481,13 @@ static u32 intel_panel_get_backlight(struct drm_device *dev, > return val; > } > > +static void intel_bdw_panel_set_backlight(struct drm_device *dev, u32 level) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; > + I915_WRITE(BLC_PWM_PCH_CTL2, val | level); > +} > + > static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -496,7 +505,9 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev, > DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); > level = intel_panel_compute_brightness(dev, pipe, level); > > - if (HAS_PCH_SPLIT(dev)) > + if (IS_BROADWELL(dev)) > + return intel_bdw_panel_set_backlight(dev, level); > + else if (HAS_PCH_SPLIT(dev)) > return intel_pch_panel_set_backlight(dev, level); > > if (is_backlight_combination_mode(dev)) { > @@ -666,7 +677,16 @@ void intel_panel_enable_backlight(struct intel_connector *connector) > POSTING_READ(reg); > I915_WRITE(reg, tmp | BLM_PWM_ENABLE); > > - if (HAS_PCH_SPLIT(dev) && > + if (IS_BROADWELL(dev)) { > + /* > + * Broadwell requires PCH override to drive the PCH > + * backlight pin. The above will configure the CPU > + * backlight pin, which we don't plan to use. > + */ > + tmp = I915_READ(BLC_PWM_PCH_CTL1); > + tmp |= BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE; > + I915_WRITE(BLC_PWM_PCH_CTL1, tmp); > + } else if (HAS_PCH_SPLIT(dev) && > !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) { > tmp = I915_READ(BLC_PWM_PCH_CTL1); > tmp |= BLM_PCH_PWM_ENABLE; > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
