On Thu, Nov 07, 2013 at 10:25:44AM +0800, Lee, Chon Ming wrote: > On 11/06 14:02, Ville Syrjälä wrote: > > > > -#define _DPIO_IREF_CTL_A 0x8040 > > > -#define _DPIO_IREF_CTL_B 0x8060 > > > -#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) > > > +#define _VLV_PLL_DW10_CH0 0x8040 > > > +#define _VLV_PLL_DW10_CH1 0x8060 > > > +#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) > > > > Configdb starts counting from DW8 at 0x8040/60, which kind of make sense > > since the first PLL block ends at DW7. > > > The spreadsheet I refer to is using DW10. The spreadsheet might be incorrect. > Looking at the register offset, it won't be anymore space left after first PLL > block. Make sense for DW8 for second PLL block. The spreadsheet is a bit weird. I was just looking at the web configdb. That at least has some sense in the offsets (apart from the ref block). The spreadsheet also uses hex numbers to count the dwords, which doesn't match what you've done for the > 8 numbers. So I'd go with the web configdb numbers since they're a bit more consistent. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
