On Tue, Nov 05, 2013 at 01:01:47PM -0800, Jesse Barnes wrote:
> On Tue, 5 Nov 2013 22:42:29 +0200
> ville.syrjala@xxxxxxxxxxxxxxx wrote:
>
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > We'll be looking at more than just mem_freq from dev_priv, so
> > just pass the whole thing.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
First two patches in this series merged to dinq, thanks.
-Daniel
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++----------
> > drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> > drivers/gpu/drm/i915/i915_sysfs.c | 13 ++++++-------
> > drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++---------------------
> > 4 files changed, 31 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 7008aac..9770c2f 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -974,15 +974,14 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
> >
> > val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
> > seq_printf(m, "max GPU freq: %d MHz\n",
> > - vlv_gpu_freq(dev_priv->mem_freq, val));
> > + vlv_gpu_freq(dev_priv, val));
> >
> > val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
> > seq_printf(m, "min GPU freq: %d MHz\n",
> > - vlv_gpu_freq(dev_priv->mem_freq, val));
> > + vlv_gpu_freq(dev_priv, val));
> >
> > seq_printf(m, "current GPU freq: %d MHz\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - (freq_sts >> 8) & 0xff));
> > + vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > } else {
> > seq_puts(m, "no P-state info available\n");
> > @@ -2725,8 +2724,7 @@ i915_max_freq_get(void *data, u64 *val)
> > return ret;
> >
> > if (IS_VALLEYVIEW(dev))
> > - *val = vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.max_delay);
> > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
> > else
> > *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -2756,7 +2754,7 @@ i915_max_freq_set(void *data, u64 val)
> > * Turbo will still be enabled, but won't go above the set value.
> > */
> > if (IS_VALLEYVIEW(dev)) {
> > - val = vlv_freq_opcode(dev_priv->mem_freq, val);
> > + val = vlv_freq_opcode(dev_priv, val);
> > dev_priv->rps.max_delay = val;
> > gen6_set_rps(dev, val);
> > } else {
> > @@ -2791,8 +2789,7 @@ i915_min_freq_get(void *data, u64 *val)
> > return ret;
> >
> > if (IS_VALLEYVIEW(dev))
> > - *val = vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.min_delay);
> > + *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
> > else
> > *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -2822,7 +2819,7 @@ i915_min_freq_set(void *data, u64 val)
> > * Turbo will still be enabled, but won't go below the set value.
> > */
> > if (IS_VALLEYVIEW(dev)) {
> > - val = vlv_freq_opcode(dev_priv->mem_freq, val);
> > + val = vlv_freq_opcode(dev_priv, val);
> > dev_priv->rps.min_delay = val;
> > valleyview_set_rps(dev, val);
> > } else {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 2aa7053..4bae871 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2412,8 +2412,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> > void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> > enum intel_sbi_destination destination);
> >
> > -int vlv_gpu_freq(int ddr_freq, int val);
> > -int vlv_freq_opcode(int ddr_freq, int val);
> > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
> > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >
> > #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
> > #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
> > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> > index cef38fd..5e81cf1 100644
> > --- a/drivers/gpu/drm/i915/i915_sysfs.c
> > +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > @@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
> > if (IS_VALLEYVIEW(dev_priv->dev)) {
> > u32 freq;
> > freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > - ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
> > + ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> > } else {
> > ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
> > }
> > @@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > return snprintf(buf, PAGE_SIZE, "%d\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.rpe_delay));
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay));
> > }
> >
> > static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> > @@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
> >
> > mutex_lock(&dev_priv->rps.hw_lock);
> > if (IS_VALLEYVIEW(dev_priv->dev))
> > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay);
> > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
> > else
> > ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> > mutex_lock(&dev_priv->rps.hw_lock);
> >
> > if (IS_VALLEYVIEW(dev_priv->dev)) {
> > - val = vlv_freq_opcode(dev_priv->mem_freq, val);
> > + val = vlv_freq_opcode(dev_priv, val);
> >
> > hw_max = valleyview_rps_max_freq(dev_priv);
> > hw_min = valleyview_rps_min_freq(dev_priv);
> > @@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
> >
> > mutex_lock(&dev_priv->rps.hw_lock);
> > if (IS_VALLEYVIEW(dev_priv->dev))
> > - ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay);
> > + ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
> > else
> > ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
> > mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> > mutex_lock(&dev_priv->rps.hw_lock);
> >
> > if (IS_VALLEYVIEW(dev)) {
> > - val = vlv_freq_opcode(dev_priv->mem_freq, val);
> > + val = vlv_freq_opcode(dev_priv, val);
> >
> > hw_max = valleyview_rps_max_freq(dev_priv);
> > hw_min = valleyview_rps_min_freq(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 865035b..f5bb9b3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3609,9 +3609,9 @@ static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
> >
> > if (pval != dev_priv->rps.cur_delay)
> > DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
> > dev_priv->rps.cur_delay,
> > - vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
> > + vlv_gpu_freq(dev_priv, pval), pval);
> >
> > dev_priv->rps.cur_delay = pval;
> > }
> > @@ -3629,10 +3629,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
> > vlv_update_rps_cur_delay(dev_priv);
> >
> > DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.cur_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
> > dev_priv->rps.cur_delay,
> > - vlv_gpu_freq(dev_priv->mem_freq, val), val);
> > + vlv_gpu_freq(dev_priv, val), val);
> >
> > if (val == dev_priv->rps.cur_delay)
> > return;
> > @@ -3641,7 +3640,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
> >
> > dev_priv->rps.cur_delay = val;
> >
> > - trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
> > + trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
> > }
> >
> > static void gen6_disable_rps_interrupts(struct drm_device *dev)
> > @@ -4070,32 +4069,27 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >
> > dev_priv->rps.cur_delay = (val >> 8) & 0xff;
> > DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.cur_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
> > dev_priv->rps.cur_delay);
> >
> > dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
> > dev_priv->rps.hw_max = dev_priv->rps.max_delay;
> > DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.max_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
> > dev_priv->rps.max_delay);
> >
> > dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
> > DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.rpe_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
> > dev_priv->rps.rpe_delay);
> >
> > dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
> > DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.min_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
> > dev_priv->rps.min_delay);
> >
> > DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> > - vlv_gpu_freq(dev_priv->mem_freq,
> > - dev_priv->rps.rpe_delay),
> > + vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
> > dev_priv->rps.rpe_delay);
> >
> > valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
> > @@ -5945,12 +5939,12 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
> > return 0;
> > }
> >
> > -int vlv_gpu_freq(int ddr_freq, int val)
> > +int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> > {
> > int div;
> >
> > /* 4 x czclk */
> > - switch (ddr_freq) {
> > + switch (dev_priv->mem_freq) {
> > case 800:
> > div = 10;
> > break;
> > @@ -5964,15 +5958,15 @@ int vlv_gpu_freq(int ddr_freq, int val)
> > return -1;
> > }
> >
> > - return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div);
> > + return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
> > }
> >
> > -int vlv_freq_opcode(int ddr_freq, int val)
> > +int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> > {
> > int mul;
> >
> > /* 4 x czclk */
> > - switch (ddr_freq) {
> > + switch (dev_priv->mem_freq) {
> > case 800:
> > mul = 10;
> > break;
> > @@ -5986,7 +5980,7 @@ int vlv_freq_opcode(int ddr_freq, int val)
> > return -1;
> > }
> >
> > - return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6;
> > + return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
> > }
> >
> > void intel_pm_init(struct drm_device *dev)
>
> Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
>
> --
> Jesse Barnes, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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