This patch introduces a sysfs interface to easily allow dynamically switch
slice config default behaviour between 1 or 2 slices.
v2: use number of slices on (1,2) instead of half or full strings.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_sysfs.c | 53 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 64 +++++++++++++++++++++++++++++++++++++--
4 files changed, 116 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 27073e8..5bd8d6f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1791,6 +1791,7 @@ struct drm_i915_file_private {
#define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
#define HAS_PSR(dev) (IS_HASWELL(dev))
+#define HAS_SLICE_SHUTDOWN(dev) (IS_HSW_GT3(dev) && i915_enable_rc6)
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index cef38fd..bf6dd95 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -117,6 +117,51 @@ static struct attribute_group rc6_attr_group = {
.name = power_group_name,
.attrs = rc6_attrs
};
+
+static ssize_t gt_slices_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct drm_minor *minor = dev_to_drm_minor(kdev);
+ struct drm_device *dev = minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ return sprintf(buf, "%s\n", I915_READ(MI_PREDICATE_RESULT_2) ==
+ LOWER_SLICE_ENABLED ? "2" : "1");
+}
+
+static ssize_t gt_slices_store(struct device *kdev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct drm_minor *minor = dev_to_drm_minor(kdev);
+ struct drm_device *dev = minor->dev;
+ int ret;
+ int slices;
+
+ ret = kstrtoint(buf, 10, &slices);
+ if (ret)
+ return ret;
+
+ ret = intel_set_gt_slices(dev, slices);
+ if (ret)
+ return ret;
+
+ return count;
+}
+
+static DEVICE_ATTR(gt_slices, S_IRUGO | S_IWUSR, gt_slices_show,
+ gt_slices_store);
+
+static struct attribute *gt_slices_attrs[] = {
+ &dev_attr_gt_slices.attr,
+ NULL
+};
+
+static struct attribute_group gt_slices_attr_group = {
+ .name = power_group_name,
+ .attrs = gt_slices_attrs
+};
+
#endif
static int l3_access_valid(struct drm_device *dev, loff_t offset)
@@ -558,6 +603,12 @@ void i915_setup_sysfs(struct drm_device *dev)
if (ret)
DRM_ERROR("RC6 residency sysfs setup failed\n");
}
+ if (HAS_SLICE_SHUTDOWN(dev)) {
+ ret = sysfs_merge_group(&dev->primary->kdev->kobj,
+ >_slices_attr_group);
+ if (ret)
+ DRM_ERROR("GT slice config sysfs setup failed\n");
+ }
#endif
if (HAS_L3_DPF(dev)) {
ret = device_create_bin_file(dev->primary->kdev, &dpf_attrs);
@@ -597,5 +648,7 @@ void i915_teardown_sysfs(struct drm_device *dev)
device_remove_bin_file(dev->primary->kdev, &dpf_attrs);
#ifdef CONFIG_PM
sysfs_unmerge_group(&dev->primary->kdev->kobj, &rc6_attr_group);
+ sysfs_unmerge_group(&dev->primary->kdev->kobj,
+ >_slices_attr_group);
#endif
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 42c3983..cf37741 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -836,6 +836,7 @@ void intel_set_power_well(struct drm_device *dev, bool enable);
void intel_enable_gt_powersave(struct drm_device *dev);
void intel_disable_gt_powersave(struct drm_device *dev);
void ironlake_teardown_rc6(struct drm_device *dev);
+int intel_set_gt_slices(struct drm_device *dev, int slices);
void intel_init_gt_slices(struct drm_device *dev);
void gen6_update_ring_freq(struct drm_device *dev);
void gen6_rps_idle(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 02d1b1f..40ab76a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3869,14 +3869,72 @@ static void gen6_enable_rps(struct drm_device *dev)
gen6_gt_force_wake_put(dev_priv);
}
-void intel_init_gt_slices(struct drm_device *dev)
+static int intel_set_gt_full(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (!IS_HSW_GT3(dev))
- return;
+ I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH);
+ /* Slices are enabled on RC6 exit */
+ gen6_gt_force_wake_get(dev_priv);
+
+ if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) ==
+ SLICE_STATUS_BOTH_ON), 2000)) {
+ DRM_ERROR("Timeout enabling full gt slices\n");
+ I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH);
+ I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
+ gen6_gt_force_wake_put(dev_priv);
+ return -ETIMEDOUT;
+ }
I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
+ gen6_gt_force_wake_put(dev_priv);
+
+ return 0;
+}
+
+static int intel_set_gt_half(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH);
+
+ /* Slices are disabled on RC6 exit */
+ gen6_gt_force_wake_get(dev_priv);
+
+ if (wait_for(((I915_READ(HSW_GT_SLICE_INFO) & SLICE_STATUS_MASK) ==
+ SLICE_STATUS_MAIN_ON), 2000)) {
+ DRM_ERROR("Timed out disabling half gt slices\n");
+ I915_WRITE(HSW_GT_SLICE_INFO, SLICE_SEL_BOTH);
+ I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
+ gen6_gt_force_wake_put(dev_priv);
+ return -ETIMEDOUT;
+ }
+ I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
+ gen6_gt_force_wake_put(dev_priv);
+ return 0;
+}
+
+int intel_set_gt_slices(struct drm_device *dev, int slices)
+{
+ if (!HAS_SLICE_SHUTDOWN(dev))
+ return -ENODEV;
+
+ switch (slices) {
+ case 1: return intel_set_gt_half(dev);
+ case 2: return intel_set_gt_full(dev);
+ default: return -EINVAL;
+ }
+}
+
+void intel_init_gt_slices(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (IS_HSW_GT3(dev))
+ I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
+
+ if (!HAS_SLICE_SHUTDOWN(dev))
+ return;
if (i915_gt_slices == 1) {
I915_WRITE(HSW_GT_SLICE_INFO, ~SLICE_SEL_BOTH);
--
1.7.11.7
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
