On Tue, 5 Nov 2013 22:42:31 +0200
ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Supposedly all current SKUs use GPLL, but there could be ones in the
> future that do not. Add (at least theoretical) support for such things.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 24 +++++++++++++++++++++++-
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index dd40925..d9b4c26 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -876,6 +876,7 @@ struct intel_gen6_power_mgmt {
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
>
> bool enabled;
> + bool gpll_enabled;
> struct delayed_work delayed_resume_work;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f5bb9b3..caec9fe 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4064,7 +4064,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> - DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
> + dev_priv->rps.gpll_enabled = val & 0x10;
> + DRM_DEBUG_DRIVER("GPLL enabled? %s\n",
> + dev_priv->rps.gpll_enabled ? "yes" : "no");
> DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
>
> dev_priv->rps.cur_delay = (val >> 8) & 0xff;
> @@ -5943,6 +5945,17 @@ int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
> {
> int div;
>
> + if (!dev_priv->rps.gpll_enabled) {
> + int hpll_freq = valleyview_get_vco(dev_priv);
> +
> + div = 0xee + (10 << 1) - val;
> +
> + if (WARN_ON(div == 0))
> + return -1;
> +
> + return DIV_ROUND_CLOSEST(hpll_freq << 1, div);
> + }
> +
> /* 4 x czclk */
> switch (dev_priv->mem_freq) {
> case 800:
> @@ -5965,6 +5978,15 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> {
> int mul;
>
> + if (!dev_priv->rps.gpll_enabled) {
> + int hpll_freq = valleyview_get_vco(dev_priv);
> +
> + if (WARN_ON(val == 0))
> + return -1;
> +
> + return 0xee + (10 << 1) - DIV_ROUND_CLOSEST(hpll_freq << 1, val);
> + }
> +
> /* 4 x czclk */
> switch (dev_priv->mem_freq) {
> case 800:
I don't think we want to add this; even though it's a small amount of
code it's totally unnecessary on real hw, and will probably just bit
rot.
--
Jesse Barnes, Intel Open Source Technology Center
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