On Tue, Nov 05, 2013 at 01:24:49PM +0200, Ville Syrjälä wrote: > On Mon, Nov 04, 2013 at 04:06:59PM -0800, Jesse Barnes wrote: > > It's possible that the CCK clock could run at a different rate than the > > DDR clock, so use the same method to get CCK as the GMBUS code does when > > calculating the new CDclk divider in the VLV display code. > > > > Reported-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > > For the series: > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Both series merged, thanks for patches and review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
