On Sat, 2 Nov 2013 21:07:52 -0700
Ben Widawsky <benjamin.widawsky@xxxxxxxxx> wrote:
> This is mostly what we have for HSW with the exceptions of:
> no writes:
> GEN6_RC1_WAKE_RATE_LIMIT
> GEN6_RC6pp_WAKE_RATE_LIMIT
> GEN6_RC1e_THRESHOLD
> GEN6_RC6p_THRESHOLD
> GEN6_RC6pp_THRESHOLD
>
> GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s
>
> Don't try to overclock, or program ring/IA frequency tables since we
> don't quite have sufficient docs yet.
>
> NOTE: These values do not reflect the changes made recently by Chris.
> Since we have no evidence yet what the proper way to tweak for this
> platform is, I think it is good to go, and can be optimized by Chris, or
> whomever, later.
>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> [danvet: Drop spurious hunk and drop TODO - having per-platform rps
> register frobbing code is in my opinion preferred, now that all the
> infrastructure functions are extracted.]
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 75 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3dd30f7..0245985 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3762,6 +3762,78 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev)
> I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
> }
>
> +static void gen8_enable_rps(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ring_buffer *ring;
> + uint32_t rc6_mask = 0, rp_state_cap;
> + int unused;
> +
> + /* 1a: Software RC state - RC0 */
> + I915_WRITE(GEN6_RC_STATE, 0);
> +
> + /* 1c & 1d: Get forcewake during program sequence. Although the driver
> + * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
> + gen6_gt_force_wake_get(dev_priv);
> +
> + /* 2a: Disable RC states. */
> + I915_WRITE(GEN6_RC_CONTROL, 0);
> +
> + rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
> +
> + /* 2b: Program RC6 thresholds.*/
> + I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> + I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + for_each_ring(ring, dev_priv, unused)
> + I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
> + I915_WRITE(GEN6_RC_SLEEP, 0);
> + I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> +
> + /* 3: Enable RC6 */
> + if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
> + rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> + DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
> + I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> + GEN6_RC_CTL_EI_MODE(1) |
> + rc6_mask);
> +
> + /* 4 Program defaults and thresholds for RPS*/
> + I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
> + I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
> + /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
> + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
> +
> + /* Docs recommend 900MHz, and 300 MHz respectively */
> + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
> + dev_priv->rps.max_delay << 24 |
> + dev_priv->rps.min_delay << 16);
> +
> + I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
> + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
> + I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
> + I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
> +
> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> + /* 5: Enable RPS */
> + I915_WRITE(GEN6_RP_CONTROL,
> + GEN6_RP_MEDIA_TURBO |
> + GEN6_RP_MEDIA_HW_NORMAL_MODE |
> + GEN6_RP_MEDIA_IS_GFX |
> + GEN6_RP_ENABLE |
> + GEN6_RP_UP_BUSY_AVG |
> + GEN6_RP_DOWN_IDLE_AVG);
> +
> + /* 6: Ring frequency + overclocking (our driver does this later */
> +
> + gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
> +
> + gen6_enable_rps_interrupts(dev);
> +
> + gen6_gt_force_wake_put(dev_priv);
> +}
> +
> static void gen6_enable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4891,6 +4963,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
>
> if (IS_VALLEYVIEW(dev)) {
> valleyview_enable_rps(dev);
> + } else if (IS_BROADWELL(dev)) {
> + gen8_enable_rps(dev);
> + gen6_update_ring_freq(dev);
> } else {
> gen6_enable_rps(dev);
> gen6_update_ring_freq(dev);
Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
--
Jesse Barnes, Intel Open Source Technology Center
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