On Mon, Nov 04, 2013 at 11:52:46AM -0800, Jesse Barnes wrote:
> On VLV/BYT, we can adjust the CDclk frequency up or down based on the
> max pixel clock we need to drive. Lowering it can save power, while
> raising it is necessary to support high resolution.
>
> Add a new callback in modeset_affected_pipes and a
> modeset_global_resources function to perform this adjustment as
> necessary.
>
> v2: use punit interface for 320 and 266 MHz CDclk adjustments (Ville)
> v3: reset GMBUS dividers too, since we changed CDclk (Ville)
> v4: jump to highest voltage when going to 400MHz CDclk (Jesse)
> v5: drop duplicate define (Ville)
> use shifts by 1 for fixed point (Ville)
> drop new callback (Daniel)
>
> Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> drivers/gpu/drm/i915/intel_display.c | 179 +++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_i2c.c | 4 -
> 3 files changed, 185 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 737d8a3..5708a6f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -363,6 +363,11 @@
> #define PUNIT_OPCODE_REG_READ 6
> #define PUNIT_OPCODE_REG_WRITE 7
>
> +#define PUNIT_REG_DSPFREQ 0x36
> +#define DSPFREQSTAT_SHIFT 30
> +#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
> +#define DSPFREQGUAR_SHIFT 14
> +#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
> #define PUNIT_REG_PWRGT_CTRL 0x60
> #define PUNIT_REG_PWRGT_STATUS 0x61
> #define PUNIT_CLK_GATE 1
> @@ -425,6 +430,7 @@
> #define DSI_PLL_N1_DIV_MASK (3 << 16)
> #define DSI_PLL_M1_DIV_SHIFT 0
> #define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
> +#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
>
> /*
> * DPIO - a special bus for various display related registers to hide behind
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 606a594..8cf42a6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3894,6 +3894,175 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> +static int valleyview_get_vco(struct drm_i915_private *dev_priv)
> +{
> + int vco;
> +
> + switch (dev_priv->mem_freq) {
> + default:
> + case 800:
> + vco = 800;
> + break;
> + case 1066:
> + vco = 1600;
> + break;
> + case 1333:
> + vco = 2000;
> + break;
> + }
> +
> + return vco;
> +}
> +
> +/* Adjust CDclk dividers to allow high res or save power if possible */
> +static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 val, cmd;
> +
> + if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
> + cmd = 2;
> + else if (cdclk == 266)
> + cmd = 1;
> + else
> + cmd = 0;
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> + val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> + val &= ~DSPFREQGUAR_MASK;
> + val |= (cmd << DSPFREQGUAR_SHIFT);
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> + if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
> + DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
> + 50)) {
> + DRM_ERROR("timed out waiting for CDclk change\n");
> + }
> + mutex_unlock(&dev_priv->rps.hw_lock);
> +
> + if (cdclk == 400) {
> + u32 divider, vco;
> +
> + vco = valleyview_get_vco(dev_priv);
> + divider = ((vco << 1) / cdclk) - 1;
> +
> + mutex_lock(&dev_priv->dpio_lock);
> + /* adjust cdclk divider */
> + val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
> + val &= ~0xf;
> + val |= divider;
> + vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
> + mutex_unlock(&dev_priv->dpio_lock);
> + }
> +
> + mutex_lock(&dev_priv->dpio_lock);
> + /* adjust self-refresh exit latency value */
> + val = vlv_bunit_read(dev_priv, 0x11);
> + val &= ~0x7f;
> +
> + /*
> + * For high bandwidth configs, we set a higher latency in the bunit
> + * so that the core display fetch happens in time to avoid underruns.
> + */
> + if (cdclk == 400)
> + val |= 0x12;
> + else
> + val |= 0xc;
I just went trawling in configdb to figure out what this does. Maybe
we should make this a bit less magic. For example:
/*
* ... set a higher self refresh exit latency ...
*/
if (cdclk == 400)
val |= 4500 / 250; /* 4.5 usec */
else
val |= 3000 / 250; /* 3.0 usec */
> + vlv_bunit_write(dev_priv, 0x11, val);
> + mutex_unlock(&dev_priv->dpio_lock);
> +
> + /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
> + intel_i2c_reset(dev);
> +}
> +
> +static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
> +{
> + int cur_cdclk, vco;
> + int divider;
> +
> + vco = valleyview_get_vco(dev_priv);
> +
> + mutex_lock(&dev_priv->dpio_lock);
> + divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
> + mutex_unlock(&dev_priv->dpio_lock);
> +
> + divider &= 0xf;
> +
> + cur_cdclk = (vco << 1) / (divider + 1);
> +
> + return cur_cdclk;
> +}
> +
> +static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
> + int max_pixclk)
> +{
> + int cur_cdclk;
> +
> + cur_cdclk = valleyview_cur_cdclk(dev_priv);
> +
> + /*
> + * Really only a few cases to deal with, as only 4 CDclks are supported:
> + * 200MHz
> + * 267MHz
> + * 320MHz
> + * 400MHz
> + * So we check to see whether we're above 90% of the lower bin and
> + * adjust if needed.
> + */
> + if (max_pixclk > 288000) {
> + return 400;
> + } else if (max_pixclk > 240000) {
> + return 320;
> + } else
> + return 266;
> + /* Looks like the 200MHz CDclk freq doesn't work on some configs */
> +}
> +
> +static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
> +{
> + struct drm_device *dev = dev_priv->dev;
> + struct intel_crtc *intel_crtc;
> + int max_pixclk = 0;
> +
> + list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
> + base.head) {
> + if (!intel_crtc->base.enabled)
> + continue;
> +
> + if (max_pixclk < intel_crtc->config.adjusted_mode.clock)
^^^^^
Maybe just write it as:
max_pixclk = max(max_pixclk, intel_crtc->config.adjusted_mode.crtc_clock);
Otherwise it's looking pretty good to me.
> + max_pixclk = intel_crtc->config.adjusted_mode.crtc_clock;
> + }
> +
> + return max_pixclk;
> +}
> +
> +static void valleyview_modeset_global_pipes(struct drm_device *dev,
> + unsigned *prepare_pipes)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc;
> + int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int cur_cdclk = valleyview_cur_cdclk(dev_priv);
> +
> + if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
> + return;
> +
> + list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
> + base.head)
> + if (intel_crtc->base.enabled)
> + *prepare_pipes |= (1 << intel_crtc->pipe);
> +}
> +
> +static void valleyview_modeset_global_resources(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + int max_pixclk = intel_mode_max_pixclk(dev_priv);
> + int cur_cdclk = valleyview_cur_cdclk(dev_priv);
> + int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> +
> + if (req_cdclk != cur_cdclk)
> + valleyview_set_cdclk(dev, req_cdclk);
> +}
> +
> static void valleyview_crtc_enable(struct drm_crtc *crtc)
> {
> struct drm_device *dev = crtc->dev;
> @@ -8844,6 +9013,13 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
> *modeset_pipes &= 1 << intel_crtc->pipe;
> *prepare_pipes &= 1 << intel_crtc->pipe;
>
> + /*
> + * See if the config requires any additional preparation, e.g.
> + * to adjust global state with pipes off.
> + */
> + if (IS_VALLEYVIEW(dev))
> + valleyview_modeset_global_pipes(dev, prepare_pipes);
> +
> DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
> *modeset_pipes, *prepare_pipes, *disable_pipes);
> }
> @@ -10329,6 +10505,9 @@ static void intel_init_display(struct drm_device *dev)
> }
> } else if (IS_G4X(dev)) {
> dev_priv->display.write_eld = g4x_write_eld;
> + } else if (IS_VALLEYVIEW(dev)) {
> + dev_priv->display.modeset_global_resources =
> + valleyview_modeset_global_resources;
> }
>
> /* Default just returns -ENODEV to indicate unsupported */
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 2ca17b1..1263409 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -87,10 +87,6 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv)
>
> BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
>
> - /* Skip setting the gmbus freq if BIOS has already programmed it */
> - if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
> - return;
> -
> /* Obtain SKU information */
> mutex_lock(&dev_priv->dpio_lock);
> hpll_freq =
> --
> 1.8.3.1
>
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--
Ville Syrjälä
Intel OTC
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