On Sun, 03 Nov 2013, Ben Widawsky <benjamin.widawsky@xxxxxxxxx> wrote:
> Broadwell PSR support is a superset of Haswell. With this simple
> register base calculation, everything that worked on HSW for eDP PSR
> should work on BDW.
Per bspec, EDP_PSR_CTL register EDP_PSR_MIN_LINK_ENTRY_TIME_* bits are
reserved/MBZ on BDW, but intel_edp_psr_enable_source() sets them.
With that fixed,
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> Note that Broadwell provides additional PSR support. This is not
> addressed at this time.
>
> v2: Make the HAS_PSR include BDW
>
> v3: Use the correct offset (I had incorrectly used one from my faulty
> brain) (Art!)
>
> v4: It helps if you git add
>
> CC: Art Runyan <arthur.j.runyan@xxxxxxxxx>
> Reviewed-by: Art Runyan <arthur.j.runyan@xxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f222eb4..dc79a0f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1808,7 +1808,7 @@ struct drm_i915_file_private {
> #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_GEN8(dev))
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev) (IS_HASWELL(dev))
> +#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff00
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65f9631..f97836e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1956,8 +1956,8 @@
> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
> #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>
> -/* HSW eDP PSR registers */
> -#define EDP_PSR_BASE(dev) 0x64800
> +/* HSW+ eDP PSR registers */
> +#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
> #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define EDP_PSR_LINK_DISABLE (0<<27)
> --
> 1.8.4.2
>
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--
Jani Nikula, Intel Open Source Technology Center
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