The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Woraround would be to use save and restore histogram register. Signed-off-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_histogram.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/display/intel_histogram.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index ad4f75607ccb..189f7ccd6df8 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -36,6 +36,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) u32 dpstbin; int i, try = 0; + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(i915, 12, 13)) + intel_de_rmw(i915, DPST_CTL(intel_crtc->pipe), + DPST_CTL_RESTORE, 0); + /* * TODO: PSR to be exited while reading the Histogram data * Set DPST_CTL Bin Reg function select to TC @@ -77,6 +82,12 @@ static void intel_histogram_handle_int_work(struct work_struct *work) histogram_event)) drm_err(&i915->drm, "sending HISTOGRAM event failed\n"); + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(i915, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(i915, DPST_CTL(intel_crtc->pipe), intel_de_read(i915, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* Enable histogram interrupt */ intel_de_rmw(i915, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, DPST_GUARD_HIST_INT_EN); @@ -140,6 +151,12 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc) /* Pipe Dithering should be enabled with GLOBAL_HIST */ intel_histogram_enable_dithering(i915, pipe); + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(i915, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(i915, DPST_CTL(intel_crtc->pipe), intel_de_read(i915, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* * enable DPST_CTL Histogram mode * Clear DPST_CTL Bin Reg function select to TC diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h index f35ea76719d8..5e24d3c5c28b 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.h +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -20,6 +20,7 @@ enum pipe; #define DPST_CTL_RESTORE REG_BIT(28) #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) #define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT REG_GENMASK(23, 16) #define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) #define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) -- 2.25.1
