On Thu, 08 Aug 2024, Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx> wrote: > Add full modeset being triggered during VRR enable/disable, specially > when panel has Adaptive sync SDP suypport. I don't understand what that is trying to say. BR, Jani. > > Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 2755ebbbb9d2..b41ea78d4c89 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5433,7 +5433,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, > PIPE_CONF_CHECK_INFOFRAME(hdmi); > PIPE_CONF_CHECK_INFOFRAME(drm); > PIPE_CONF_CHECK_DP_VSC_SDP(vsc); > - PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); > + if(!fastset) > + PIPE_CONF_CHECK_DP_AS_SDP(as_sdp); > > PIPE_CONF_CHECK_X(sync_mode_slaves_mask); > PIPE_CONF_CHECK_I(master_transcoder); -- Jani Nikula, Intel
