On Fri, Oct 25, 2013 at 06:42:35PM -0700, Ian Romanick wrote: > Since the Mesa merge window is closing soon, I'm finally getting back on > this. I've pushed a rebase of my old Mesa branch to my fd.o repo > > http://cgit.freedesktop.org/~idr/mesa/log/?h=robustness3 > > I have a couple questions... > > 1. Has any of this landed an a kernel tree anywhere? Afaik everything but the actual ioctl and i-g-t testcase has landed. > 2. Has any support code landed in a libdrm tree anywhere? Dunno whether Mika has libdrm patches. Since mesa is the only expected user I'd just go with putting the ioctl wrapper (using the drmIoctl helper) into mesa itself, that get rids of a dep for merging this support. > 3. What method should I use to detect that the kernel has support? In > early discussions, reset notification was only going to be available on > some GPUs, so there was a getparam to detect actual availability. I > guess now it's just based on kernel version? Usually we add a new feature flag to get get_param ioctl if there's no natural way otherwise for userspace to figure this out (usually by calling the new ioctl and disabling the feature if that doesn't work). -Daniel > > It looks like I should just need to update df87cdd and 61dad8e in my > Mesa tree. > > On 07/03/2013 07:22 AM, Mika Kuoppala wrote: > > This ioctl returns reset stats for specified context. > > > > The struct returned contains context loss counters. > > > > reset_count: all resets across all contexts > > batch_active: active batches lost on resets > > batch_pending: pending batches lost on resets > > > > v2: get rid of state tracking completely and deliver only counts. Idea > > from Chris Wilson. > > > > v3: fix commit message > > > > v4: default context handled inside i915_gem_contest_get_hang_stats > > > > v5: reset_count only for priviledged process > > > > v6: ctx=0 needs CAP_SYS_ADMIN for batch_* counters (Chris Wilson) > > > > v7: context hang stats never returns NULL > > > > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > Cc: Ian Romanick <idr@xxxxxxxxxxxxxxx> > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Daniel Vetter <daniel.vetter@xxxxxxxx> > > --- > > drivers/gpu/drm/i915/i915_dma.c | 1 + > > drivers/gpu/drm/i915/i915_drv.c | 34 ++++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > include/uapi/drm/i915_drm.h | 17 +++++++++++++++++ > > 4 files changed, 54 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > > index 0e22142..d1a006f 100644 > > --- a/drivers/gpu/drm/i915/i915_dma.c > > +++ b/drivers/gpu/drm/i915/i915_dma.c > > @@ -1889,6 +1889,7 @@ struct drm_ioctl_desc i915_ioctls[] = { > > DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED), > > DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED), > > DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED), > > + DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED), > > }; > > > > int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > > index 33cb973..0d4e3a8 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.c > > +++ b/drivers/gpu/drm/i915/i915_drv.c > > @@ -1350,3 +1350,37 @@ int i915_reg_read_ioctl(struct drm_device *dev, > > > > return 0; > > } > > + > > +int i915_get_reset_stats_ioctl(struct drm_device *dev, > > + void *data, struct drm_file *file) > > +{ > > + struct drm_i915_private *dev_priv = dev->dev_private; > > + struct drm_i915_reset_stats *args = data; > > + struct i915_ctx_hang_stats *hs; > > + int ret; > > + > > + if (args->ctx_id == 0 && !capable(CAP_SYS_ADMIN)) > > + return -EPERM; > > + > > + ret = mutex_lock_interruptible(&dev->struct_mutex); > > + if (ret) > > + return ret; > > + > > + hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id); > > + if (IS_ERR(hs)) { > > + mutex_unlock(&dev->struct_mutex); > > + return PTR_ERR(hs); > > + } > > + > > + if (capable(CAP_SYS_ADMIN)) > > + args->reset_count = i915_reset_count(&dev_priv->gpu_error); > > + else > > + args->reset_count = 0; > > + > > + args->batch_active = hs->batch_active; > > + args->batch_pending = hs->batch_pending; > > + > > + mutex_unlock(&dev->struct_mutex); > > + > > + return 0; > > +} > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 1def049..0ca98fa 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2021,6 +2021,8 @@ extern int intel_enable_rc6(const struct drm_device *dev); > > extern bool i915_semaphore_is_enabled(struct drm_device *dev); > > int i915_reg_read_ioctl(struct drm_device *dev, void *data, > > struct drm_file *file); > > +int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file); > > > > /* overlay */ > > #ifdef CONFIG_DEBUG_FS > > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h > > index 923ed7f..29b07fd 100644 > > --- a/include/uapi/drm/i915_drm.h > > +++ b/include/uapi/drm/i915_drm.h > > @@ -198,6 +198,7 @@ typedef struct _drm_i915_sarea { > > #define DRM_I915_GEM_SET_CACHING 0x2f > > #define DRM_I915_GEM_GET_CACHING 0x30 > > #define DRM_I915_REG_READ 0x31 > > +#define DRM_I915_GET_RESET_STATS 0x32 > > > > #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) > > #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) > > @@ -247,6 +248,7 @@ typedef struct _drm_i915_sarea { > > #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) > > #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) > > #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) > > +#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) > > > > /* Allow drivers to submit batchbuffers directly to hardware, relying > > * on the security mechanisms provided by hardware. > > @@ -981,4 +983,19 @@ struct drm_i915_reg_read { > > __u64 offset; > > __u64 val; /* Return value */ > > }; > > + > > +struct drm_i915_reset_stats { > > + __u32 ctx_id; > > + __u32 flags; > > + > > + /* For all contexts */ > > + __u32 reset_count; > > + > > + /* For this context */ > > + __u32 batch_active; > > + __u32 batch_pending; > > + > > + __u32 pad; > > +}; > > + > > #endif /* _UAPI_I915_DRM_H_ */ > > > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
