== Series Details == Series: Implement CMRR Support (rev8) URL : https://patchwork.freedesktop.org/series/126443/ State : warning == Summary == Error: dim checkpatch failed 92bb97f71e5a drm/i915: Define and compute Transcoder CMRR registers -:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects? #45: FILE: drivers/gpu/drm/i915/display/intel_display.c:5061: +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) -:45: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues #45: FILE: drivers/gpu/drm/i915/display/intel_display.c:5061: +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) total: 0 errors, 0 warnings, 2 checks, 119 lines checked 510f4b1dbdb6 drm/i915: Add Enable/Disable for CMRR based on VRR state b46ecb3a76b0 drm/i915: Compute CMRR and calculate vtotal 0c2dda3d0bda Add refresh rate divider to struct representing AS SDP d290c6cbc14d drm/i915/display: Add support for pack and unpack e1f1d198d476 drm/i915/display: Compute Adaptive sync SDP params 3c0f9940bc19 drm/i915/display: Compute vrr vsync params
