On Fri, 11 Oct 2013 22:24:41 +0300 ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Supposedly VLV uses the CTG+ style frame counter registers instead of > the old gen3/4 style. Add the magic offset to the correct registers. > > We should already be taking the correct codepaths for > .get_vblank_counter() and .get_scanout_position(). > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 96fd2ce..9964de6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3339,17 +3339,17 @@ > * } while (high1 != high2); > * frame = (high1 << 8) | low1; > */ > -#define _PIPEAFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x70040) > +#define _PIPEAFRAMEHIGH 0x70040 > #define PIPE_FRAME_HIGH_MASK 0x0000ffff > #define PIPE_FRAME_HIGH_SHIFT 0 > -#define _PIPEAFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x70044) > +#define _PIPEAFRAMEPIXEL 0x70044 > #define PIPE_FRAME_LOW_MASK 0xff000000 > #define PIPE_FRAME_LOW_SHIFT 24 > #define PIPE_PIXEL_MASK 0x00ffffff > #define PIPE_PIXEL_SHIFT 0 > /* GM45+ just has to be different */ > -#define _PIPEA_FRMCOUNT_GM45 0x70040 > -#define _PIPEA_FLIPCOUNT_GM45 0x70044 > +#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040) > +#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044) > #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) > > /* Cursor A & B regs */ > @@ -3480,10 +3480,10 @@ > #define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) > #define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) > #define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) > -#define _PIPEBFRAMEHIGH (dev_priv->info->display_mmio_offset + 0x71040) > -#define _PIPEBFRAMEPIXEL (dev_priv->info->display_mmio_offset + 0x71044) > -#define _PIPEB_FRMCOUNT_GM45 0x71040 > -#define _PIPEB_FLIPCOUNT_GM45 0x71044 > +#define _PIPEBFRAMEHIGH 0x71040 > +#define _PIPEBFRAMEPIXEL 0x71044 > +#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040) > +#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044) > > > /* Display B control */ Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
