2013/10/9 <ville.syrjala@xxxxxxxxxxxxxxx>: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > We want to be able to use the masks to decode the register contents > regardless of the hardware generation. So just expand the masks to > cover all available bits, even if those are reserved on some > generations. > > v2: Don't extend WM1_LP_SR_MASK so far, for the *future* > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I checked BSpec and it seems these values were all already wrong for Haswell! Most masks were lacking 1 bit. I think we were not using these maks on HSW, so we're probably fine. Maybe adding a comment saying "the masks change from Gen to Gen, but we keep the big backwards-compatible values" could be a good thing. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_reg.h | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index c246727..cab709d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3251,11 +3251,11 @@ > > /* define the Watermark register on Ironlake */ > #define WM0_PIPEA_ILK 0x45100 > -#define WM0_PIPE_PLANE_MASK (0x7f<<16) > +#define WM0_PIPE_PLANE_MASK (0xffff<<16) > #define WM0_PIPE_PLANE_SHIFT 16 > -#define WM0_PIPE_SPRITE_MASK (0x3f<<8) > +#define WM0_PIPE_SPRITE_MASK (0xff<<8) > #define WM0_PIPE_SPRITE_SHIFT 8 > -#define WM0_PIPE_CURSOR_MASK (0x1f) > +#define WM0_PIPE_CURSOR_MASK (0xff) > > #define WM0_PIPEB_ILK 0x45104 > #define WM0_PIPEC_IVB 0x45200 > @@ -3265,9 +3265,9 @@ > #define WM1_LP_LATENCY_MASK (0x7f<<24) > #define WM1_LP_FBC_MASK (0xf<<20) > #define WM1_LP_FBC_SHIFT 20 > -#define WM1_LP_SR_MASK (0x1ff<<8) > +#define WM1_LP_SR_MASK (0x7ff<<8) > #define WM1_LP_SR_SHIFT 8 > -#define WM1_LP_CURSOR_MASK (0x3f) > +#define WM1_LP_CURSOR_MASK (0xff) > #define WM2_LP_ILK 0x4510c > #define WM2_LP_EN (1<<31) > #define WM3_LP_ILK 0x45110 > -- > 1.8.1.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
