On Thu, 10 Oct 2013 21:58:50 +0100
Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote:
> As we delay the initial RPS enabling (upon boot and after resume), there
> is a chance that we may start to render and trigger RPS boosts before we
> set up the punit. Any changes we make could result in inconsistent
> hardware state, with a danger of causing undefined behaviour. However,
> as the boosting is a optional tweak to RPS, we can simply ignore it
> whilst RPS is not yet enabled.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Cc: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 26 ++++++++++++++++----------
> 2 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 640bff2..e0152e7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -874,6 +874,7 @@ struct intel_gen6_power_mgmt {
> int last_adj;
> enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
>
> + bool enabled;
> struct delayed_work delayed_resume_work;
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6ffeb04..8070a07 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3435,22 +3435,26 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
> void gen6_rps_idle(struct drm_i915_private *dev_priv)
> {
> mutex_lock(&dev_priv->rps.hw_lock);
> - if (dev_priv->info->is_valleyview)
> - valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> - else
> - gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> - dev_priv->rps.last_adj = 0;
> + if (dev_priv->rps.enabled) {
> + if (dev_priv->info->is_valleyview)
> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> + else
> + gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
> + dev_priv->rps.last_adj = 0;
> + }
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> void gen6_rps_boost(struct drm_i915_private *dev_priv)
> {
> mutex_lock(&dev_priv->rps.hw_lock);
> - if (dev_priv->info->is_valleyview)
> - valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
> - else
> - gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
> - dev_priv->rps.last_adj = 0;
> + if (dev_priv->rps.enabled) {
> + if (dev_priv->info->is_valleyview)
> + valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
> + else
> + gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
> + dev_priv->rps.last_adj = 0;
> + }
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
> @@ -4657,6 +4661,7 @@ void intel_disable_gt_powersave(struct drm_device *dev)
> valleyview_disable_rps(dev);
> else
> gen6_disable_rps(dev);
> + dev_priv->rps.enabled = false;
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
> }
> @@ -4676,6 +4681,7 @@ static void intel_gen6_powersave_work(struct work_struct *work)
> gen6_enable_rps(dev);
> gen6_update_ring_freq(dev);
> }
> + dev_priv->rps.enabled = true;
> mutex_unlock(&dev_priv->rps.hw_lock);
> }
>
Yeah looks good. Probably better than doing a sync on the delayed work
too, since that'll take over 1s.
Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
--
Jesse Barnes, Intel Open Source Technology Center
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