On Fri, Oct 04, 2013 at 11:07:19AM -0700, Jesse Barnes wrote:
> On Fri, 4 Oct 2013 20:32:25 +0300
> ville.syrjala@xxxxxxxxxxxxxxx wrote:
>
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > The VGACNTRL register contains a bunch of other stuff besides
> > the VGA_DISP_DISABLE bit. When we write the register we always set those
> > other bits to zero, so normally the current check would work.
> >
> > However on HSW disabling and re-enabling the power well will reset the
> > VGACNTRL register to its default value, which has several of the other
> > bits set as well.
> >
> > So only look at the VGA_DISP_DISABLE bit when checking whether the VGA
> > plane needs re-disabling.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0ba0af4..925a387 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -10659,7 +10659,7 @@ void i915_redisable_vga(struct drm_device *dev)
> > (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
> > return;
> >
> > - if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> > + if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
> > DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> > i915_disable_vga(dev);
> > i915_disable_vga_mem(dev);
>
> Looks good.
>
> Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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