On Thu, 3 Oct 2013 19:38:26 +0300 Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > On Fri, Sep 27, 2013 at 12:34:31PM +0300, Ville Syrjälä wrote: > > On Thu, Sep 26, 2013 at 02:39:14PM -0700, Jesse Barnes wrote: > > > This fixes resume on my test platform, since I think some DPIO bits need > > > recalibration. > > > > > > References: https://bugs.freedesktop.org/show_bug.cgi?id=69166 > > > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > > > --- > > > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ > > > 1 file changed, 13 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > > index f52e6d4..320f729 100644 > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > @@ -1359,6 +1359,17 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, > > > assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); > > > } > > > > > > +static void intel_init_dpio(struct drm_device *dev) > > > +{ > > > + struct drm_i915_private *dev_priv = dev->dev_private; > > > + > > > + if (!IS_VALLEYVIEW(dev)) > > > + return; > > > + > > > + /* Reset in case DPIO was stuck across suspend/resume or boot */ > > > + I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_RESET); > > > > This will deassert the common lane reset, so the comment is confusing, > > as is the name we have given this bit. > > And the commit subject and text is also confusing in the same way. > > And we should do this after setting up the CRI clock. So I'm still confused by this. The bit is called "CMNRST", which doesn't say anything to me about deasserting common lane reset, unless you mean setting it to 0, which the docs imply. But here we're setting it to on 1. But I guess you're talking about something than the other gunit register HAS? At any rate, it's not confusing to me now, though it may become so if I try to read a few more docs... -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
