On Thu, Oct 03, 2013 at 11:16:17PM +0800, Chon Ming Lee wrote:
> During system boot up, by default, the power gate for render, media and
> display well still power gated. Normally, BIOS will turn off the power
> gate. In the BIOS-less system, the driver need to turn off the power
> gate very early during driver load.
>
> v2: Move this to intel_uncore_sanitize to allow it to get call during
> resume path. (Daniel)
> v3: Remove redundant write 0 to DPIO_CTL, and use DPIO_RESET instead of
> just 0x1 (Ville)
> Add turn of power gate for display 2d/render well/media well.
> v4: Remove toggle cmnreset in intel_uncore_sanitize. Cmnreset should
> toggle after CRI clock source has been selected. Jesse DPIO reset patch
> which toggle the cmnreset in intel_modeset_init_hw() should handle it.
> (Ville)
>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx>
Looks OK as a short term solution.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++++++
> drivers/gpu/drm/i915/intel_uncore.c | 16 ++++++++++++++++
> 2 files changed, 25 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3432de4..f14310b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -361,6 +361,15 @@
> #define PUNIT_OPCODE_REG_READ 6
> #define PUNIT_OPCODE_REG_WRITE 7
>
> +#define PUNIT_REG_PWRGT_CTRL 0x60
> +#define PUNIT_REG_PWRGT_STATUS 0x61
> +#define PUNIT_CLK_GATE 1
> +#define PUNIT_PWR_RESET 2
> +#define PUNIT_PWR_GATE 3
> +#define RENDER_PWRGT (PUNIT_PWR_GATE << 0)
> +#define MEDIA_PWRGT (PUNIT_PWR_GATE << 2)
> +#define DISP2D_PWRGT (PUNIT_PWR_GATE << 6)
> +
> #define PUNIT_REG_GPU_LFM 0xd3
> #define PUNIT_REG_GPU_FREQ_REQ 0xd4
> #define PUNIT_REG_GPU_FREQ_STS 0xd8
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index f2753d9..288a3a6 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -301,10 +301,26 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev)
>
> void intel_uncore_sanitize(struct drm_device *dev)
> {
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 reg_val;
> +
> intel_uncore_forcewake_reset(dev);
>
> /* BIOS often leaves RC6 enabled, but disable it for hw init */
> intel_disable_gt_powersave(dev);
> +
> + /* Turn off power gate, require especially for the BIOS less system */
> + if (IS_VALLEYVIEW(dev)) {
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> + reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
> +
> + if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
> + vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
> +
> + mutex_unlock(&dev_priv->rps.hw_lock);
> +
> + }
> }
>
> /*
> --
> 1.7.7.6
>
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--
Ville Syrjälä
Intel OTC
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