== Series Details == Series: ALPM AUX Wake Configuration (rev2) URL : https://patchwork.freedesktop.org/series/127954/ State : warning == Summary == Error: dim checkpatch failed b9c0b09fc5df drm/i915/alpm: Add ALPM register definitions -:38: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #38: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:304: +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0) -:39: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #39: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:305: +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1) -:40: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #40: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:306: +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2) -:41: WARNING:LONG_LINE: line length of 113 exceeds 100 columns #41: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:307: +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3) -:44: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #44: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:310: +#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val) -:47: WARNING:LONG_LINE: line length of 158 exceeds 100 columns #47: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:313: +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) -:49: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #49: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:315: +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) -:54: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #54: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:320: +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) -:56: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #56: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:322: +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) -:58: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #58: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:324: +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) -:60: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #60: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:326: +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) -:63: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #63: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:329: +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) -:69: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #69: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:335: +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) -:71: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #71: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:337: +#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) -:73: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #73: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:339: +#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) -:76: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #76: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:342: +#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) -:80: WARNING:LONG_LINE: line length of 158 exceeds 100 columns #80: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:346: +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) -:82: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #82: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:348: +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) -:87: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #87: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:353: +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) -:89: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #89: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:355: +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) -:91: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #91: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:357: +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) -:93: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #93: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:359: +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) -:96: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #96: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:362: +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) -:101: WARNING:LONG_LINE: line length of 158 exceeds 100 columns #101: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:367: +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) -:103: WARNING:LONG_LINE: line length of 109 exceeds 100 columns #103: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:369: +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) -:108: WARNING:LONG_LINE: line length of 124 exceeds 100 columns #108: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:374: +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) -:110: WARNING:LONG_LINE: line length of 128 exceeds 100 columns #110: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:376: +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) -:112: WARNING:LONG_LINE: line length of 115 exceeds 100 columns #112: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:378: +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) -:114: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #114: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:380: +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) -:117: WARNING:LONG_LINE: line length of 138 exceeds 100 columns #117: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:383: +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) -:122: WARNING:LONG_LINE: line length of 169 exceeds 100 columns #122: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:388: +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN) -:124: WARNING:LONG_LINE: line length of 133 exceeds 100 columns #124: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:390: +#define PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) -:126: WARNING:LONG_LINE: line length of 133 exceeds 100 columns #126: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:392: +#define PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) -:128: WARNING:LONG_LINE: line length of 133 exceeds 100 columns #128: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:394: +#define PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val) REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val) total: 0 errors, 34 warnings, 0 checks, 107 lines checked 477e883f0cc9 drm/i915/psr: Add alpm_parameters struct 75ce0887cd1d drm/i915/alpm: Calculate ALPM Entry check 8f84c9560452 drm/i915/alpm: Alpm aux wake configuration for lnl
