On Tue, Oct 01, 2013 at 10:41:38AM -0700, Jesse Barnes wrote: > The global integrated clock source bit resides in DPLL B on VLV, but we > were treating it as a per-pipe resource. It needs to be set whenever > any PLL is active, so pull setting the bit out of vlv_update_pll and > into vlv_enable_pll. Also add a vlv_disable_pll to prevent disabling it > when pipe B shuts down. > > I'm guessing on the references here, I expect this to bite any config > where multiple displays are active or displays are moved from pipe to > pipe. > > v2: re-add bits in vlv_update_pll to keep from confusing the state checker > v3: use enum pipe checks (Daniel) > set CRI clock source early (Ville) > consistently set CRI clock source everywhere (Ville) > v4: drop unnecessary setting of bit in vlv enable pll (Ville) > > References: https://bugs.freedesktop.org/show_bug.cgi?id=67245 > References: https://bugs.freedesktop.org/show_bug.cgi?id=69693 > Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++--- > 1 file changed, 26 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 29b9387..a08b7d2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1466,6 +1466,20 @@ static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > POSTING_READ(DPLL(pipe)); > } > > +static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) > +{ > + u32 val = 0; > + > + /* Make sure the pipe isn't still relying on us */ > + assert_pipe_disabled(dev_priv, pipe); > + > + /* Leave integrated clock source enabled */ > + if (pipe == PIPE_B) > + val = DPLL_INTEGRATED_CRI_CLK_VLV; > + I915_WRITE(DPLL(pipe), val); > + POSTING_READ(DPLL(pipe)); > +} > + > void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) > { > u32 port_mask; > @@ -3875,7 +3889,9 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) > if (encoder->post_disable) > encoder->post_disable(encoder); > > - if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) > + if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) > + vlv_disable_pll(dev_priv, pipe); > + else if (!IS_VALLEYVIEW(dev)) > i9xx_disable_pll(dev_priv, pipe); > > intel_crtc->active = false; > @@ -4615,9 +4631,9 @@ static void vlv_update_pll(struct intel_crtc *crtc) > /* Enable DPIO clock input */ > dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | > DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; > - if (pipe) > + /* We should never disable this, set it here for state tracking */ > + if (pipe == PIPE_B) > dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; > - > dpll |= DPLL_VCO_ENABLE; > crtc->config.dpll_hw_state.dpll = dpll; > > @@ -10279,10 +10295,17 @@ void i915_disable_vga_mem(struct drm_device *dev) > > void intel_modeset_init_hw(struct drm_device *dev) > { > + struct drm_i915_private *dev_priv = dev->dev_private; > + > intel_prepare_ddi(dev); > > intel_init_clock_gating(dev); > > + /* Enable the CRI clock source so we can get at the display */ > + if (IS_VALLEYVIEW(dev)) > + I915_WRITE(DPLL(1), I915_READ(DPLL(1)) | > + DPLL_INTEGRATED_CRI_CLK_VLV); > + > mutex_lock(&dev->struct_mutex); > intel_enable_gt_powersave(dev); > mutex_unlock(&dev->struct_mutex); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
