On Wed, Sep 25, 2013 at 03:47:51PM +0800, Chon Ming Lee wrote: > Fix the typo in previous commit for DP 1.62 divisor. > drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2 > > v2: sigh, the m1 div is 3. > > Reported-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx> > Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx> Ok, I'll try this one ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
