From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
The p2 divider on VLV needs to be even when it's > 10. The current code
to make that happen is rather weird. Just make the step size adjustement
in the for loop decrement step.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c5f0794..330fefc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -687,9 +687,8 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
/* based on hardware requirement, prefer smaller n to precision */
for (clock.n = limit->n.min; clock.n <= ((refclk) / minupdate); clock.n++) {
for (clock.p1 = limit->p1.max; clock.p1 > limit->p1.min; clock.p1--) {
- for (clock.p2 = limit->p2.p2_fast+1; clock.p2 > 0; clock.p2--) {
- if (clock.p2 > 10)
- clock.p2--;
+ for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0;
+ clock.p2 -= clock.p2 > 10 ? 2 : 1) {
clock.p = clock.p1 * clock.p2;
/* based on hardware requirement, prefer bigger m1,m2 values */
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
--
1.8.1.5
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