Hm, that sounds a bit more like the ddx is having fun with rendering. Have you tried switching the backed from to either SNA or UXA? Also adding relevant mailing lists ... -Daniel On Sun, Sep 22, 2013 at 7:06 PM, Thomas Richter <thor@xxxxxxxxxxxxxxxxx> wrote: > Hi folks, hi Daniel, > > there is still an issue with flicker on panning with the 835GM chipset. As > already explained, the flicker only appears if the panning position > satisfies certain alignment constraints, in specific. As long as the plane > pointer is aligned to 64 byte boundaries, everything works correctly. > > I tried now to add a parameter to the kernel to adjust the watermark level > of the chipset and see whether this makes any difference with regards to the > flicker. However, it does not. It seems that the trouble is not there. > > However, I noticed something interesting: If I use a non-native mode of the > display, i.e. enable the scaling feature of the DVO, everything works, and > no flicker ever appears. However, in these situations the resolution is also > lower than that of the native display, and hence the issue may also be > related to the PLL clock. > > I also noticed that if I invert the display, i.e. use the rotation feature, > even in the native resolution, nothing flickers, though panning is rather > slow. > > Does this somehow ring a bell? Can I somehow force the driver to use the > same logic for the regular display as for the inverted display to avoid the > flicker? > > Any help would be appreciated. > > Greetings, > Thomas > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
