Re: [PATCH] [v2] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF

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On Thu, Sep 19, 2013 at 11:01:40AM -0700, Ben Widawsky wrote:
> We'd only ever used this define to denote whether or not we have the
> dynamic parity feature (DPF) and never to determine whether or not L3
> exists. Baytrail is a good example of where L3 exists, and not DPF.
> 
> This patch provides clarify in the code for future use cases which might
> want to actually query whether or not L3 exists.
> 
> v2: Add /* DPF == dynamic parity feature */
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>

Ok, I've slurped all the kernel patches in. Like I've said I'd very much
welcome a little testcase to inject an error and exercise this stuff a
bit, if it's not a horrendous amount of work to get going.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 5 +++--
>  drivers/gpu/drm/i915/i915_gem.c         | 2 +-
>  drivers/gpu/drm/i915/i915_irq.c         | 4 ++--
>  drivers/gpu/drm/i915/i915_sysfs.c       | 4 ++--
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++---
>  5 files changed, 11 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 015df52..09a5c82 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1691,8 +1691,9 @@ struct drm_i915_file_private {
>  
>  #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
>  
> -#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> -#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_GPU_CACHE(dev))
> +/* DPF == dynamic parity feature */
> +#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
> +#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
>  
>  #define GT_FREQUENCY_MULTIPLIER 50
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 18d07d7..7859f91 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4260,7 +4260,7 @@ int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
>  	u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
>  	int i, ret;
>  
> -	if (!HAS_L3_GPU_CACHE(dev) || !remap_info)
> +	if (!HAS_L3_DPF(dev) || !remap_info)
>  		return 0;
>  
>  	ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1c7f6ab..cfaf434 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -960,7 +960,7 @@ static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
>  {
>  	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
>  
> -	if (!HAS_L3_GPU_CACHE(dev))
> +	if (!HAS_L3_DPF(dev))
>  		return;
>  
>  	spin_lock(&dev_priv->irq_lock);
> @@ -2292,7 +2292,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
>  	pm_irqs = gt_irqs = 0;
>  
>  	dev_priv->gt_irq_mask = ~0;
> -	if (HAS_L3_GPU_CACHE(dev)) {
> +	if (HAS_L3_DPF(dev)) {
>  		/* L3 parity interrupt is always unmasked. */
>  		dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
>  		gt_irqs |= GT_PARITY_ERROR(dev);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index deb8787..7b4c79c 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -97,7 +97,7 @@ static struct attribute_group rc6_attr_group = {
>  
>  static int l3_access_valid(struct drm_device *dev, loff_t offset)
>  {
> -	if (!HAS_L3_GPU_CACHE(dev))
> +	if (!HAS_L3_DPF(dev))
>  		return -EPERM;
>  
>  	if (offset % 4 != 0)
> @@ -525,7 +525,7 @@ void i915_setup_sysfs(struct drm_device *dev)
>  			DRM_ERROR("RC6 residency sysfs setup failed\n");
>  	}
>  #endif
> -	if (HAS_L3_GPU_CACHE(dev)) {
> +	if (HAS_L3_DPF(dev)) {
>  		ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
>  		if (ret)
>  			DRM_ERROR("l3 parity sysfs setup failed\n");
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 958b7d8..b67104a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -569,7 +569,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>  	if (INTEL_INFO(dev)->gen >= 6)
>  		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>  
> -	if (HAS_L3_GPU_CACHE(dev))
> +	if (HAS_L3_DPF(dev))
>  		I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
>  
>  	return ret;
> @@ -997,7 +997,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
>  
>  	spin_lock_irqsave(&dev_priv->irq_lock, flags);
>  	if (ring->irq_refcount++ == 0) {
> -		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> +		if (HAS_L3_DPF(dev) && ring->id == RCS)
>  			I915_WRITE_IMR(ring,
>  				       ~(ring->irq_enable_mask |
>  					 GT_PARITY_ERROR(dev)));
> @@ -1019,7 +1019,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
>  
>  	spin_lock_irqsave(&dev_priv->irq_lock, flags);
>  	if (--ring->irq_refcount == 0) {
> -		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
> +		if (HAS_L3_DPF(dev) && ring->id == RCS)
>  			I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
>  		else
>  			I915_WRITE_IMR(ring, ~0);
> -- 
> 1.8.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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