On Fri, 06 Sep 2013, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> On CTG+ read out the pipe bpp setting from hardware and fill it into
> pipe config. Also check it appropriately.
>
> v2: Don't do the pipe_bpp extraction inside the PCH only code block on
> ILK+.
> Avoid the PIPECONF read as we already have read it for the
> PIPECONF_EANBLE check.
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 17 +++++++++++++++++
> drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 060ea50..9305fb6 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1268,6 +1268,23 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
> flags |= DRM_MODE_FLAG_NVSYNC;
>
> pipe_config->adjusted_mode.flags |= flags;
> +
> + switch (temp & TRANS_DDI_BPC_MASK) {
> + case TRANS_DDI_BPC_6:
> + pipe_config->pipe_bpp = 18;
> + break;
> + case TRANS_DDI_BPC_8:
> + pipe_config->pipe_bpp = 24;
> + break;
> + case TRANS_DDI_BPC_10:
> + pipe_config->pipe_bpp = 30;
> + break;
> + case TRANS_DDI_BPC_12:
> + pipe_config->pipe_bpp = 36;
> + break;
> + default:
> + break;
> + }
> }
>
> static void intel_ddi_destroy(struct drm_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2aac205..35ad910 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4999,6 +4999,22 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> return false;
>
> + if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
> + switch (tmp & PIPECONF_BPC_MASK) {
> + case PIPECONF_6BPC:
> + pipe_config->pipe_bpp = 18;
> + break;
> + case PIPECONF_8BPC:
> + pipe_config->pipe_bpp = 24;
> + break;
> + case PIPECONF_10BPC:
> + pipe_config->pipe_bpp = 30;
> + break;
> + default:
> + break;
> + }
> + }
> +
> intel_get_pipe_timings(crtc, pipe_config);
>
> i9xx_get_pfit_config(crtc, pipe_config);
> @@ -5899,6 +5915,23 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> if (!(tmp & PIPECONF_ENABLE))
> return false;
>
> + switch (tmp & PIPECONF_BPC_MASK) {
> + case PIPECONF_6BPC:
> + pipe_config->pipe_bpp = 18;
> + break;
> + case PIPECONF_8BPC:
> + pipe_config->pipe_bpp = 24;
> + break;
> + case PIPECONF_10BPC:
> + pipe_config->pipe_bpp = 30;
> + break;
> + case PIPECONF_12BPC:
> + pipe_config->pipe_bpp = 36;
> + break;
> + default:
> + break;
> + }
> +
> if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
> struct intel_shared_dpll *pll;
>
> @@ -8630,6 +8663,9 @@ intel_pipe_config_compare(struct drm_device *dev,
> PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
> PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
>
> + if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
> + PIPE_CONF_CHECK_I(pipe_bpp);
> +
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> #undef PIPE_CONF_CHECK_FLAGS
> --
> 1.8.1.5
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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--
Jani Nikula, Intel Open Source Technology Center
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