From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
In some Haswell machines we're seeing a full system hang while calling
haswell_crtc_enable. Ville bisected the problem to the following
commit:
commit 90a8864320b2a9f91e5b5d561924a4bb70b90dcc
Author: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Date: Fri May 3 17:23:45 2013 -0300
drm/i915: set FORCE_ARB_IDLE_PLANES workaround
After some BSpec-digging I discovered that we don't implement one of
the workarounds mentioned in the description of bit 31 of PRI_CTL,
SPR_CTL and CUR_CTL. This patch implements the workaround, which makes
the problem go away on my machine. Also notice that the workaround
implementation is almost a revert of the commit mentioned above, but
it still allows LP watermarks to be used.
Thanks to Ville for the help debugging the issue and for doing the
bisect.
Cc: stable@xxxxxxxxxxxxxxx
Credits-to: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c0e0cf..6e9c44a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3359,6 +3359,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
struct intel_encoder *encoder;
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
+ uint32_t wm_dbg_val;
WARN_ON(!crtc->enabled);
@@ -3391,6 +3392,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_ddi_set_pipe_settings(crtc);
intel_ddi_enable_transcoder_func(crtc);
+ /* Workaround described in PRI_CTL, CUR_CTL and SPR_CTL bit 31. */
+ wm_dbg_val = I915_READ(WM_DBG);
+ I915_WRITE(WM_DBG, wm_dbg_val | WM_DBG_DISALLOW_MULTIPLE_LP |
+ WM_DBG_DISALLOW_MAXFIFO | WM_DBG_DISALLOW_SPRITE);
+
intel_update_watermarks(crtc);
intel_enable_pipe(dev_priv, pipe,
intel_crtc->config.has_pch_encoder, false);
@@ -3421,6 +3427,9 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
* happening.
*/
intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+ /* Second part of the WM_DBG workaround. */
+ I915_WRITE(WM_DBG, wm_dbg_val);
}
static void ironlake_pfit_disable(struct intel_crtc *crtc)
--
1.8.3.1
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