On Tue, Sep 10, 2013 at 04:00:03PM +0100, Damien Lespiau wrote:
> On Wed, Sep 04, 2013 at 06:25:22PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Currently most of the watermark code looks at crtc->mode which is the
> > user requested mode. The only piece of information there that is
> > relevant is hdisplay, the rest must come from adjusted_mode. Convert
> > all of the code to use requested_mode and adjusted_mode from
> > pipe config appropriately.
>
> I'm not quite sure why you single out hdisplay here, would you mind
> explaining why?
The watermark code is usually interested in the primary plane width.
requested_mode.hdisplay is the closest thing we have at the momemnt.
>
> --
> Damien
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 55 ++++++++++++++++++++++++-----------------
> > 1 file changed, 33 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index af1f4de..48d93d3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1109,7 +1109,7 @@ static void pineview_update_wm(struct drm_device *dev)
> >
> > crtc = single_enabled_crtc(dev);
> > if (crtc) {
> > - int clock = crtc->mode.clock;
> > + int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
> > int pixel_size = crtc->fb->bits_per_pixel / 8;
> >
> > /* Display SR */
> > @@ -1170,6 +1170,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> > int *cursor_wm)
> > {
> > struct drm_crtc *crtc;
> > + const struct drm_display_mode *adjusted_mode;
> > int htotal, hdisplay, clock, pixel_size;
> > int line_time_us, line_count;
> > int entries, tlb_miss;
> > @@ -1181,9 +1182,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
> > return false;
> > }
> >
> > - htotal = crtc->mode.htotal;
> > - hdisplay = crtc->mode.hdisplay;
> > - clock = crtc->mode.clock;
> > + adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
> > + clock = adjusted_mode->clock;
> > + htotal = adjusted_mode->htotal;
> > + hdisplay = to_intel_crtc(crtc)->config.requested_mode.hdisplay;
> > pixel_size = crtc->fb->bits_per_pixel / 8;
> >
> > /* Use the small buffer method to calculate plane watermark */
> > @@ -1254,6 +1256,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> > int *display_wm, int *cursor_wm)
> > {
> > struct drm_crtc *crtc;
> > + const struct drm_display_mode *adjusted_mode;
> > int hdisplay, htotal, pixel_size, clock;
> > unsigned long line_time_us;
> > int line_count, line_size;
> > @@ -1266,9 +1269,10 @@ static bool g4x_compute_srwm(struct drm_device *dev,
> > }
> >
> > crtc = intel_get_crtc_for_plane(dev, plane);
> > - hdisplay = crtc->mode.hdisplay;
> > - htotal = crtc->mode.htotal;
> > - clock = crtc->mode.clock;
> > + adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
> > + clock = adjusted_mode->clock;
> > + htotal = adjusted_mode->htotal;
> > + hdisplay = to_intel_crtc(crtc)->config.requested_mode.hdisplay;
> > pixel_size = crtc->fb->bits_per_pixel / 8;
> >
> > line_time_us = (htotal * 1000) / clock;
> > @@ -1307,7 +1311,7 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
> > if (!intel_crtc_active(crtc))
> > return false;
> >
> > - clock = crtc->mode.clock; /* VESA DOT Clock */
> > + clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
> > pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
> >
> > entries = (clock / 1000) * pixel_size;
> > @@ -1492,9 +1496,11 @@ static void i965_update_wm(struct drm_device *dev)
> > if (crtc) {
> > /* self-refresh has much higher latency */
> > static const int sr_latency_ns = 12000;
> > - int clock = crtc->mode.clock;
> > - int htotal = crtc->mode.htotal;
> > - int hdisplay = crtc->mode.hdisplay;
> > + const struct drm_display_mode *adjusted_mode =
> > + &to_intel_crtc(crtc)->config.adjusted_mode;
> > + int clock = adjusted_mode->clock;
> > + int htotal = adjusted_mode->htotal;
> > + int hdisplay = to_intel_crtc(crtc)->config.requested_mode.hdisplay;
> > int pixel_size = crtc->fb->bits_per_pixel / 8;
> > unsigned long line_time_us;
> > int entries;
> > @@ -1570,7 +1576,7 @@ static void i9xx_update_wm(struct drm_device *dev)
> > if (IS_GEN2(dev))
> > cpp = 4;
> >
> > - planea_wm = intel_calculate_wm(crtc->mode.clock,
> > + planea_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
> > wm_info, fifo_size, cpp,
> > latency_ns);
> > enabled = crtc;
> > @@ -1584,7 +1590,7 @@ static void i9xx_update_wm(struct drm_device *dev)
> > if (IS_GEN2(dev))
> > cpp = 4;
> >
> > - planeb_wm = intel_calculate_wm(crtc->mode.clock,
> > + planeb_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
> > wm_info, fifo_size, cpp,
> > latency_ns);
> > if (enabled == NULL)
> > @@ -1611,9 +1617,11 @@ static void i9xx_update_wm(struct drm_device *dev)
> > if (HAS_FW_BLC(dev) && enabled) {
> > /* self-refresh has much higher latency */
> > static const int sr_latency_ns = 6000;
> > - int clock = enabled->mode.clock;
> > - int htotal = enabled->mode.htotal;
> > - int hdisplay = enabled->mode.hdisplay;
> > + const struct drm_display_mode *adjusted_mode =
> > + &to_intel_crtc(enabled)->config.adjusted_mode;
> > + int clock = adjusted_mode->clock;
> > + int htotal = adjusted_mode->htotal;
> > + int hdisplay = to_intel_crtc(crtc)->config.requested_mode.hdisplay;
> > int pixel_size = enabled->fb->bits_per_pixel / 8;
> > unsigned long line_time_us;
> > int entries;
> > @@ -1673,7 +1681,8 @@ static void i830_update_wm(struct drm_device *dev)
> > if (crtc == NULL)
> > return;
> >
> > - planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
> > + planea_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
> > + &i830_wm_info,
> > dev_priv->display.get_fifo_size(dev, 0),
> > 4, latency_ns);
> > fwater_lo = I915_READ(FW_BLC) & ~0xfff;
> > @@ -1745,6 +1754,7 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
> > int *fbc_wm, int *display_wm, int *cursor_wm)
> > {
> > struct drm_crtc *crtc;
> > + const struct drm_display_mode *adjusted_mode;
> > unsigned long line_time_us;
> > int hdisplay, htotal, pixel_size, clock;
> > int line_count, line_size;
> > @@ -1757,9 +1767,10 @@ static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
> > }
> >
> > crtc = intel_get_crtc_for_plane(dev, plane);
> > - hdisplay = crtc->mode.hdisplay;
> > - htotal = crtc->mode.htotal;
> > - clock = crtc->mode.clock;
> > + adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
> > + clock = adjusted_mode->clock;
> > + htotal = adjusted_mode->htotal;
> > + hdisplay = to_intel_crtc(crtc)->config.requested_mode.hdisplay;
> > pixel_size = crtc->fb->bits_per_pixel / 8;
> >
> > line_time_us = (htotal * 1000) / clock;
> > @@ -2902,7 +2913,7 @@ sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
> > return false;
> > }
> >
> > - clock = crtc->mode.clock;
> > + clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
> >
> > /* Use the small buffer method to calculate the sprite watermark */
> > entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
> > @@ -2937,7 +2948,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
> > }
> >
> > crtc = intel_get_crtc_for_plane(dev, plane);
> > - clock = crtc->mode.clock;
> > + clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
> > if (!clock) {
> > *sprite_wm = 0;
> > return false;
> > --
> > 1.8.1.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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