From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Add a function for emitting masked register writes.
Note that the mask is implemented through bvyte enables,
so can only mask off aligned 8bit sets of bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dsb.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 4ef799c087b4..6be353fdc7fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -234,6 +234,24 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
}
}
+static u32 intel_dsb_mask_to_byte_en(u32 mask)
+{
+ return (!!(mask & 0xff000000) << 3 |
+ !!(mask & 0x00ff0000) << 2 |
+ !!(mask & 0x0000ff00) << 1 |
+ !!(mask & 0x000000ff) << 0);
+}
+
+/* Note: mask implemented via byte enables! */
+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val)
+{
+ intel_dsb_emit(dsb, val,
+ (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) |
+ (intel_dsb_mask_to_byte_en(mask) << DSB_BYTE_EN_SHIFT) |
+ i915_mmio_reg_offset(reg));
+}
+
void intel_dsb_noop(struct intel_dsb *dsb, int count)
{
int i;
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 5a08bc21beda..983b0d58ad44 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -19,6 +19,8 @@ void intel_dsb_finish(struct intel_dsb *dsb);
void intel_dsb_cleanup(struct intel_dsb *dsb);
void intel_dsb_reg_write(struct intel_dsb *dsb,
i915_reg_t reg, u32 val);
+void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
+ i915_reg_t reg, u32 mask, u32 val);
void intel_dsb_noop(struct intel_dsb *dsb, int count);
void intel_dsb_commit(struct intel_dsb *dsb,
bool wait_for_vblank);
--
2.39.3
