From: Ben Widawsky <ben@xxxxxxxxxxxx>
Turn on hardware contexts for Ironlake. This leaves the code in an
awkward place where renderctx accomplishes nothing, but the code
compiles and runs, and it makes the series overall more bisectable.
Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Tested-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> # X still works!
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2ef59e..6e3a9a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1630,7 +1630,7 @@ struct drm_i915_file_private {
#define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
-#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index fbbe3ea..aeb2012 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -106,6 +106,9 @@ static int get_context_size(struct drm_device *dev)
u32 reg;
switch (INTEL_INFO(dev)->gen) {
+ case 5:
+ ret = ILK_CXT_TOTAL_SIZE;
+ break;
case 6:
reg = I915_READ(CXT_SIZE);
ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7f2da3..1c41ef3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1765,6 +1765,7 @@
* doesn't need saving on GT1
*/
#define CXT_SIZE 0x21a0
+#define ILK_CXT_TOTAL_SIZE (1 * PAGE_SIZE)
#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
--
1.7.9.5
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