From: Ben Widawsky <ben@xxxxxxxxxxxx>
This patch starts the migration to the core context code for Ironlake
renderctx. It is an excellent place for a bisection point due to
complaining hardware, though notice that our sample size is quite
limited given that only machines with RC6 turned on could notice
problems.
NOTE: As mentioned in a previous commit, this removes an MI_FLUSH. If
issues occur, try adding that to the end of mi_set_context before
complaining.
Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Tested-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> # X still works!
---
drivers/gpu/drm/i915/i915_gem_context.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3a677ac..fbbe3ea 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -581,24 +581,5 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
int ironlake_setup_rc6_hw_context(struct drm_i915_private *dev_priv)
{
- struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
- int ret;
-
- ret = intel_ring_begin(ring, 6);
- if (ret)
- return ret;
-
- intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
- intel_ring_emit(ring, MI_SET_CONTEXT);
- intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx.obj) |
- MI_MM_SPACE_GTT |
- MI_SAVE_EXT_STATE_EN |
- MI_RESTORE_EXT_STATE_EN |
- MI_RESTORE_INHIBIT);
- intel_ring_emit(ring, MI_SUSPEND_FLUSH);
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_emit(ring, MI_FLUSH);
- intel_ring_advance(ring);
-
- return 0;
+ return do_switch(&dev_priv->ips.renderctx);
}
--
1.7.9.5
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