On Thu, 05 Sep 2013, Chon Ming Lee <chon.ming.lee@xxxxxxxxx> wrote:
> The patch doesn't contain functional change, but is to prepare for
> future platform which has different DPIO phy. The additional pipe
> parameter will use to select which phy to target for.
>
> Signed-off-by: Chon Ming Lee <chon.ming.lee@xxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> v2: Update the commit message and add static for the new function.
> (Jani/Ville)
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++------
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++----------------
> drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++----------
> drivers/gpu/drm/i915/intel_hdmi.c | 48 +++++++++++++++++-------------
> drivers/gpu/drm/i915/intel_sideband.c | 18 ++++++++---
> 6 files changed, 99 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a6f4cb5..9ac4e31 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1610,27 +1610,27 @@ static int i915_dpio_info(struct seq_file *m, void *data)
> seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
>
> seq_printf(m, "DPIO_DIV_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_DIV_A));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A));
> seq_printf(m, "DPIO_DIV_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_DIV_B));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B));
>
> seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_REFSFR_A));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A));
> seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_REFSFR_B));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B));
>
> seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A));
> seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B));
>
> seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_A));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A));
> seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n",
> - vlv_dpio_read(dev_priv, _DPIO_LPF_COEFF_B));
> + vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B));
>
> seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
> - vlv_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
> + vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE));
>
> mutex_unlock(&dev_priv->dpio_lock);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 769c138..e357995 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2282,8 +2282,8 @@ u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
> void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> -u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
> -void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
> +u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
> +void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
> u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> enum intel_sbi_destination destination);
> void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d88057e..bac7152 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4354,7 +4354,8 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
> }
> }
>
> -static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
> +static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
> + pipe)
> {
> u32 reg_val;
>
> @@ -4362,24 +4363,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
> * PLLB opamp always calibrates to max value of 0x3f, force enable it
> * and set it to a reasonable value instead.
> */
> - reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
> + reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
> reg_val &= 0xffffff00;
> reg_val |= 0x00000030;
> - vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
> + reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
> reg_val &= 0x8cffffff;
> reg_val = 0x8c000000;
> - vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
> + reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
> reg_val &= 0xffffff00;
> - vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
>
> - reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
> + reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
> reg_val &= 0x00ffffff;
> reg_val |= 0xb0000000;
> - vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
> }
>
> static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
> @@ -4445,18 +4446,18 @@ static void vlv_update_pll(struct intel_crtc *crtc)
>
> /* PLL B needs special handling */
> if (pipe)
> - vlv_pllb_recal_opamp(dev_priv);
> + vlv_pllb_recal_opamp(dev_priv, pipe);
>
> /* Set up Tx target for periodic Rcomp update */
> - vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
> + vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
>
> /* Disable target IRef on PLL */
> - reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
> + reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
> reg_val &= 0x00ffffff;
> - vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
>
> /* Disable fast lock */
> - vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
> + vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
>
> /* Set idtafcrecal before PLL is enabled */
> mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> @@ -4470,48 +4471,48 @@ static void vlv_update_pll(struct intel_crtc *crtc)
> * Note: don't use the DAC post divider as it seems unstable.
> */
> mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> - vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
> + vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
>
> mdiv |= DPIO_ENABLE_CALIBRATION;
> - vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
> + vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
>
> /* Set HBR and RBR LPF coefficients */
> if (crtc->config.port_clock == 162000 ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
> - vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
> 0x009f0003);
> else
> - vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
> 0x00d0000f);
>
> if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
> /* Use SSC source */
> if (!pipe)
> - vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> 0x0df40000);
> else
> - vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> 0x0df70000);
> } else { /* HDMI or VGA */
> /* Use bend source */
> if (!pipe)
> - vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> 0x0df70000);
> else
> - vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
> + vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
> 0x0df40000);
> }
>
> - coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
> + coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
> coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
> if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
> intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
> coreclk |= 0x01000000;
> - vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
> + vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
>
> - vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
>
> /* Enable DPIO clock input */
> dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index c192dbb..d6eba38 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1746,16 +1746,16 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
>
> mutex_lock(&dev_priv->dpio_lock);
>
> - val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
> + val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
> val = 0;
> if (pipe)
> val |= (1<<21);
> else
> val &= ~(1<<21);
> val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
> + vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
>
> mutex_unlock(&dev_priv->dpio_lock);
>
> @@ -1769,26 +1769,29 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> int port = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
>
> if (!IS_VALLEYVIEW(dev))
> return;
>
> /* Program Tx lane resets to default */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
> DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
> DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> DPIO_PCS_CLK_SOFT_RESET);
>
> /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
> - vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> @@ -1923,10 +1926,13 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
> struct drm_device *dev = intel_dp_to_dev(intel_dp);
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(dport->base.base.crtc);
> unsigned long demph_reg_value, preemph_reg_value,
> uniqtranscale_reg_value;
> uint8_t train_set = intel_dp->train_set[0];
> int port = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
>
> switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
> case DP_TRAIN_PRE_EMPHASIS_0:
> @@ -2002,14 +2008,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
> }
>
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
> uniqtranscale_reg_value);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
> - vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
> - vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
> mutex_unlock(&dev_priv->dpio_lock);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 4148cc8..70c716e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1079,35 +1079,35 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
>
> /* Enable clock channels for this port */
> mutex_lock(&dev_priv->dpio_lock);
> - val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
> + val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
> val = 0;
> if (pipe)
> val |= (1<<21);
> else
> val &= ~(1<<21);
> val |= 0x001000c4;
> - vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
> + vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
>
> /* HDMI 1.0V-2dB */
> - vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port),
> 0x2b245f5f);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
> 0x5578b83a);
> - vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port),
> 0x0c782040);
> - vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port),
> 0x2b247878);
> - vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
> 0x00002000);
> - vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
> DPIO_TX_OCALINIT_EN);
>
> /* Program lane clock */
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port),
> 0x00760018);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
> 0x00400888);
> mutex_unlock(&dev_priv->dpio_lock);
>
> @@ -1121,30 +1121,33 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> int port = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
>
> if (!IS_VALLEYVIEW(dev))
> return;
>
> /* Program Tx lane resets to default */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
> DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
> DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
> DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
> (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
> DPIO_PCS_CLK_SOFT_RESET);
>
> /* Fix up inter-pair skew failure */
> - vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
> - vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
> - vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
>
> - vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
> 0x00002000);
> - vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
> + vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
> DPIO_TX_OCALINIT_EN);
> mutex_unlock(&dev_priv->dpio_lock);
> }
> @@ -1153,12 +1156,15 @@ static void intel_hdmi_post_disable(struct intel_encoder *encoder)
> {
> struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + struct intel_crtc *intel_crtc =
> + to_intel_crtc(encoder->base.crtc);
> int port = vlv_dport_to_channel(dport);
> + int pipe = intel_crtc->pipe;
>
> /* Reset lanes to avoid HDMI flicker (VLV w/a) */
> mutex_lock(&dev_priv->dpio_lock);
> - vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
> - vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000);
> + vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060);
> mutex_unlock(&dev_priv->dpio_lock);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 0a41670..acd1cfe 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -157,19 +157,27 @@ void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> PUNIT_OPCODE_REG_WRITE, reg, &val);
> }
>
> -u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)
> +static u32 vlv_get_phy_port(enum pipe pipe)
> +{
> + u32 port = IOSF_PORT_DPIO;
> +
> + WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
> +
> + return port;
> +}
> +
> +u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> {
> u32 val = 0;
>
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
> + vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
> DPIO_OPCODE_REG_READ, reg, &val);
> -
> return val;
> }
>
> -void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
> +void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_DPIO,
> + vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
> DPIO_OPCODE_REG_WRITE, reg, &val);
> }
>
> --
> 1.7.7.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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