On Mon, Sep 02, 2013 at 09:24:26PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> We don't want to try to push the hardware beyond it's capabilities,
> so check the pixel clock against the display core clock limit. Do
> it for pre-gen4 for now since that's where we alread have the double
> wide pixel clock limit check.
>
> Let's assume that when double wide mode is enabled the max
> pixel clock limit is also doubled.
>
> FIXME: panel fitter downscaling probably affects the limit on
> non-pch platforms too, so we'd need another version of
> ilk_pipe_pixel_rate() to figure that out.
>
> FIXME: should check the limits on all platforms. Also sprites
> affect the max allowed pixel rate on some platforms, so we need
> to eventually tie all the planes and pipes into one check in
> the future. But we need plane state pre-compute before that can
> happen.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ea33468..040e0ef 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4140,6 +4140,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> return -EINVAL;
> }
>
> + /* FIXME should check pixel clock limits on all platforms */
We do by failing to find the pll. The fun is to move all that code into
the pipe computation stage. The second part of the fun is that on newer
platforms dotclock limits are all encoder specific, so we need to shovel
them into encoder callbacks anyway.
I don't know whether there are any additional pixel clock limits on top of
what the plls can handle, but at least I haven't spotted them yet ...
-Daniel
> if (INTEL_INFO(dev)->gen < 4) {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int clock_limit =
> @@ -4153,8 +4154,13 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
> * the only reason for the pipe == PIPE_A check?
> */
> if (crtc->pipe == PIPE_A &&
> - adjusted_mode->clock > clock_limit * 9 / 10)
> + adjusted_mode->clock > clock_limit * 9 / 10) {
> + clock_limit *= 2;
> pipe_config->double_wide = true;
> + }
> +
> + if (adjusted_mode->clock > clock_limit * 9 / 10)
> + return -EINVAL;
> }
>
> /* Cantiga+ cannot handle modes with a hsync front porch of 0.
> --
> 1.8.1.5
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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