From: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
MTL requires the PORT_CTL_WIDTH, TRANS_DDI_FUNC_CTL and DDI_BUF_CTL
to be filled with 4 lanes for TMDS mode.
This patch enables D2D link and fills PORT_WIDTH in appropriate
registers.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
Signed-off-by: Taylor, Clinton A <clinton.a.taylor@xxxxxxxxx>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 48 +++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 2 +
2 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1efa3b6f4101..a5a0b76c1b10 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -542,6 +542,8 @@ intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
temp |= TRANS_DDI_HDMI_SCRAMBLING;
if (crtc_state->hdmi_high_tmds_clock_ratio)
temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
} else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
temp |= (crtc_state->fdi_lanes - 1) << 1;
@@ -3142,6 +3144,10 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
if (has_buf_trans_select(dev_priv))
hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
+ /* e. Enable D2D Link for C10/C20 Phy */
+ if (DISPLAY_VER(dev_priv) >= 14)
+ mtl_ddi_enable_d2d(encoder);
+
encoder->set_signal_levels(encoder, crtc_state);
/* Display WA #1143: skl,kbl,cfl */
@@ -3187,13 +3193,39 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
*
* On ADL_P the PHY link rate and lane count must be programmed but
* these are both 0 for HDMI.
+ *
+ * But MTL onwards HDMI2.1 is supported and in TMDS mode this
+ * is always filled with 4 lanes, already set in the crtc_state.
+ * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
- buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
- if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
- drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
- buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ u32 ddi_buf = 0;
+ u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
+ u32 port_buf = 0;
+
+ port_buf |= XELPDP_PORT_WIDTH(lane_count);
+
+ if (intel_bios_encoder_lane_reversal(encoder->devdata))
+ port_buf |= XELPDP_PORT_REVERSAL;
+
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0, port_buf);
+
+ ddi_buf |= DDI_BUF_CTL_ENABLE |
+ DDI_PORT_WIDTH(lane_count);
+
+ intel_de_write(dev_priv, DDI_BUF_CTL(port),
+ dig_port->saved_port_bits | ddi_buf);
+
+ /* i. Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
+ intel_wait_ddi_buf_active(dev_priv, port);
+ } else {
+ buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+ if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
+ drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
+ buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ }
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
}
- intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3702,7 +3734,11 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
fallthrough;
case TRANS_DDI_MODE_SELECT_DVI:
pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
- pipe_config->lane_count = 4;
+ if (DISPLAY_VER(dev_priv) >= 14)
+ pipe_config->lane_count =
+ ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
+ else
+ pipe_config->lane_count = 4;
break;
case TRANS_DDI_MODE_SELECT_DP_SST:
if (encoder->type == INTEL_OUTPUT_EDP)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 82c9ba8f44b6..4c89f706481b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6751,6 +6751,8 @@ enum skl_power_gate {
#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
+#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
| TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
--
2.34.1
