From: Simon Que <sque@xxxxxxxxxxxx> If the firmware did not initialize the backlight PWM registers, set up a default PWM frequency of 200 Hz. This is determined using the following formula: freq = refclk / (128 * pwm_max) The PWM register allows the max PWM value to be set. So we want to use the formula, where freq = 200: pwm_max = refclk / (128 * freq) This patch will, in the case of missing PWM register initialization values, look for the reference clock frequency. Based on that, it sets an appropriate max PWM value for a frequency of 200 Hz. If no refclk frequency is found, the max PWM will be zero, which results in no change to the PWM registers. BUG=chrome-os-partner:5570 TEST=x86 backlight works smoothly w/o dev mode Change-Id: I4219ab8a2481afbcc3586288594b066fcc6c8294 Signed-off-by: Simon Que <sque@xxxxxxxxxxxx> Reviewed-on: https://gerrit.chromium.org/gerrit/11629 Reviewed-by: Bryan Freed <bfreed@xxxxxxxxxxxx> Reviewed-by: Sameer Nanda <snanda@xxxxxxxxxxxx> [marcheu: Fixed up for dev_priv->dev and regfile transition] Signed-off-by: Stéphane Marchesin <marcheu@xxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_panel.c | 39 ++++++++++++++++++++++++++++++++------ 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index bee8cb6..affd930 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -35,6 +35,12 @@ #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ +/* These are used to calculate a reasonable default when firmware has not + * configured a maximum PWM frequency, with 200Hz as the current default target. + */ +#define DEFAULT_BACKLIGHT_PWM_FREQ 200 +#define BACKLIGHT_REFCLK_DIVISOR 128 + void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -130,13 +136,34 @@ static int is_backlight_combination_mode(struct drm_device *dev) return 0; } +static void i915_set_default_max_backlight(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + u32 refclk_freq_mhz = 0; + u32 max_pwm; + + if (HAS_PCH_SPLIT(dev_priv->dev)) + refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; + else if (dev_priv->lvds_use_ssc) + refclk_freq_mhz = dev_priv->lvds_ssc_freq; + + max_pwm = refclk_freq_mhz * 1000000 / + (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ); + + if (HAS_PCH_SPLIT(dev_priv->dev)) + dev_priv->regfile.saveBLC_PWM_CTL2 = max_pwm << 16; + else if (IS_PINEVIEW(dev_priv->dev)) + dev_priv->regfile.saveBLC_PWM_CTL = max_pwm << 17; + else + dev_priv->regfile.saveBLC_PWM_CTL = max_pwm << 16; +} + static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; u32 val; - /* Restore the CTL value if it lost, e.g. GPU reset */ - + /* Restore the CTL value if it was lost, e.g. GPU reset */ if (HAS_PCH_SPLIT(dev_priv->dev)) { val = I915_READ(BLC_PWM_PCH_CTL2); if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { @@ -191,11 +218,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev) max = _intel_panel_get_max_backlight(dev); if (max == 0) { - /* XXX add code here to query mode clock or hardware clock - * and program max PWM appropriately. + /* If backlight PWM registers have not been set, set them to + * default backlight PWM settings. */ - pr_warn_once("fixme: max PWM is zero\n"); - return 1; + i915_set_default_max_backlight(dev); + max = i915_read_blc_pwm_ctl(dev); } DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
