From: Stéphane Marchesin <marcheu@xxxxxxxxxxxx> It's basically the same deal as the RC6+ issues on ivy bridge (https://gerrit.chromium.org/gerrit/#/c/42655/) except this time with RC6 on sandy bridge. Like last time the core of the issue is that the existing timings don't work 100% with our voltage regulator, so once in a couple suspend/resumes the kernel will print a warning message about the GPU not getting out of RC6. Luckily this time the shared timings are already working (from the ivy bridge work) so we only need to adjust the one RC6-specific timing, GEN6_RC6_THRESHOLD. Just like with the RC6+ change, I couldn't see any measurable power difference with an idle lumpy. BUG=chromium:235116 TEST=ran the power_Resume a bunch on stumpy, didn't see an RC6 error TEST=tested lumpy for power regressions on idle Change-Id: I0e1be040e0e156cd38d6c396e237d4a01a16a6a2 Reviewed-on: https://gerrit.chromium.org/gerrit/57868 Reviewed-by: Vincent Palatin <vpalatin@xxxxxxxxxxxx> Commit-Queue: Stéphane Marchesin <marcheu@xxxxxxxxxxxx> Tested-by: Stéphane Marchesin <marcheu@xxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1b487cb..8105d10 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2572,7 +2572,7 @@ static void gen6_enable_rps(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP, 0); I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); - I915_WRITE(GEN6_RC6_THRESHOLD, 50000); + I915_WRITE(GEN6_RC6_THRESHOLD, 150000); I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
