From: Daniel Kurtz <djkurtz@xxxxxxxxxxxx> i915 gmbus writes at 400kHz should now work properly. So, enable 400kHz and the native gmbus algorithm by default, but limit to known high speed devices: * atmel_mxt devices on vga ddc * atmel_mxt devices (app mode and bootloader) on panel ddc After further testing, this can be enabled for all devices and ddc adapters. Signed-off-by: Daniel Kurtz <djkurtz@xxxxxxxxxxxx> BUG=chromium-os:26118,chrome-os-partner:8547,chrome-os-partner:8732 TEST=compiles clean; i915 driver successfully communicates to i2c devices on the vga and panel ddc adapters. Tested using an atmel i2c touchpad and atmel_mxt_ts driver. TEST=place valid atmel mxt firmware at /lib/firmware/maxtouch.fw time echo 1 > update_fw Check that firmware update succeeds, and that the time is less than 18s. time echo 1 > update_fw real 0m17.923s user 0m0.000s sys 0m0.188s This is a squash of three commits onto v3.4-rc5+danvet/intel-drm-next: Change-Id: Id911a732409b06a4b0a654270d548929e2887582 Reviewed-on: https://gerrit.chromium.org/gerrit/17938 Change-Id: Ide237fbe6c33b17395d8398af1b691db69eb3036 Reviewed-on: https://gerrit.chromium.org/gerrit/18425 Change-Id: Ic5741b98b30c522acd3bee0a92041e08993e950e Reviewed-on: https://gerrit.chromium.org/gerrit/21833 --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_i2c.c | 10 +++++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 59afb7e..27ef35a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -865,6 +865,7 @@ #define GMBUS_RATE_50KHZ (1<<8) #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ +#define GMBUS_RATE_MASK (3<<8) #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ #define GMBUS_PORT_DISABLED 0 #define GMBUS_PORT_SSC 1 @@ -875,6 +876,7 @@ #define GMBUS_PORT_DPD 6 /* HDMID */ #define GMBUS_PORT_RESERVED 7 /* 7 reserved */ #define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) +#define GMBUS_PORT_MASK 7 #define GMBUS1 0x5104 /* command/status */ #define GMBUS_SW_CLR_INT (1<<31) #define GMBUS_SW_RDY (1<<30) diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 3ef5af1..364204f 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -332,6 +332,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct drm_i915_private *dev_priv = bus->dev_priv; int i, reg_offset; int ret = 0; + u32 gmbus0; mutex_lock(&dev_priv->gmbus_mutex); @@ -342,7 +343,14 @@ gmbus_xfer(struct i2c_adapter *adapter, reg_offset = dev_priv->gpio_mmio_base; - I915_WRITE(GMBUS0 + reg_offset, bus->reg0); + /* Hack to use 400kHz only for atmel_mxt i2c devices on ddc ports */ + gmbus0 = bus->reg0; + if (((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_VGADDC && + msgs[0].addr == 0x4b) || + ((gmbus0 & GMBUS_PORT_MASK) == GMBUS_PORT_PANEL && + (msgs[0].addr == 0x4a || msgs[0].addr == 0x26))) + gmbus0 = (gmbus0 & ~GMBUS_RATE_MASK) | GMBUS_RATE_400KHZ; + I915_WRITE(GMBUS0 + reg_offset, gmbus0); for (i = 0; i < num; i++) { u32 gmbus2; -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
