On Mon, 30 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@xxxxxxxxx> wrote: > A new step of 480MHz has been added on SKUs that have an RPL-U > device id. This particular step is to support 120Hz panels > more efficiently. > > This patchset adds a new table to include this new CDCLK > step. Details can be found in BSpec entry 55409. > > Create a new sub-platform to identify RPL-U which will enable > us to make the differentiation during CDCLK initialization. Thanks, pushed the series to drm-intel-next. BR, Jani. > > Furthermore, we need to make a distinction between ES (Engineering > Sample) and QS (Quality Sample) parts as this change comes only > to QS parts. This version of the patch does not include this change > as we are yet to make a decision if this particular part needs > to be upstreamed.(see comments on revision 2) > > Chaitanya Kumar Borah (2): > drm/i915: Add RPL-U sub platform > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U > > drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > include/drm/i915_pciids.h | 12 ++++++---- > 5 files changed, 44 insertions(+), 4 deletions(-) -- Jani Nikula, Intel Open Source Graphics Center
