Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
---
lib/drmtest.c | 28 ++--
lib/drmtest.h | 6 +-
tests/.gitignore | 2 +-
tests/Makefile.am | 2 +-
tests/gem_cacheing.c | 303 ---------------------------------------
tests/gem_caching.c | 303 +++++++++++++++++++++++++++++++++++++++
tests/gem_partial_pwrite_pread.c | 2 +-
tests/gem_pread.c | 2 +-
tests/gem_pread_after_blit.c | 4 +-
tests/gem_pwrite.c | 2 +-
tests/gem_pwrite_pread.c | 12 +-
11 files changed, 333 insertions(+), 333 deletions(-)
delete mode 100644 tests/gem_cacheing.c
create mode 100644 tests/gem_caching.c
diff --git a/lib/drmtest.c b/lib/drmtest.c
index f546784..cae07a2 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -380,56 +380,56 @@ skip:
return num_rings;
}
-struct local_drm_i915_gem_cacheing {
+struct local_drm_i915_gem_caching {
uint32_t handle;
- uint32_t cacheing;
+ uint32_t caching;
};
#define LOCAL_DRM_I915_GEM_SET_CACHEING 0x2f
#define LOCAL_DRM_I915_GEM_GET_CACHEING 0x30
#define LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING \
- DRM_IOW(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_SET_CACHEING, struct local_drm_i915_gem_cacheing)
+ DRM_IOW(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_SET_CACHEING, struct local_drm_i915_gem_caching)
#define LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING \
- DRM_IOWR(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_GET_CACHEING, struct local_drm_i915_gem_cacheing)
+ DRM_IOWR(DRM_COMMAND_BASE + LOCAL_DRM_I915_GEM_GET_CACHEING, struct local_drm_i915_gem_caching)
-int gem_has_cacheing(int fd)
+int gem_has_caching(int fd)
{
- struct local_drm_i915_gem_cacheing arg;
+ struct local_drm_i915_gem_caching arg;
int ret;
arg.handle = gem_create(fd, 4096);
if (arg.handle == 0)
return 0;
- arg.cacheing = 0;
+ arg.caching = 0;
ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg);
gem_close(fd, arg.handle);
return ret == 0;
}
-int gem_set_cacheing(int fd, uint32_t handle, int cacheing)
+int gem_set_caching(int fd, uint32_t handle, int caching)
{
- struct local_drm_i915_gem_cacheing arg;
+ struct local_drm_i915_gem_caching arg;
int ret;
arg.handle = handle;
- arg.cacheing = cacheing;
+ arg.caching = caching;
ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_SET_CACHEING, &arg);
return ret == 0 ? 0 : -errno;
}
-int gem_get_cacheing(int fd, uint32_t handle)
+uint32_t gem_get_caching(int fd, uint32_t handle)
{
- struct local_drm_i915_gem_cacheing arg;
+ struct local_drm_i915_gem_caching arg;
int ret;
arg.handle = handle;
- arg.cacheing = 0;
+ arg.caching = 0;
ret = ioctl(fd, LOCAL_DRM_IOCTL_I915_GEM_GET_CACHEING, &arg);
assert(ret == 0);
- return arg.cacheing;
+ return arg.caching;
}
uint32_t gem_open(int fd, uint32_t name)
diff --git a/lib/drmtest.h b/lib/drmtest.h
index 8320dbe..773beaa 100644
--- a/lib/drmtest.h
+++ b/lib/drmtest.h
@@ -53,9 +53,9 @@ bool gem_has_bsd(int fd);
bool gem_has_blt(int fd);
bool gem_has_vebox(int fd);
int gem_get_num_rings(int fd);
-int gem_has_cacheing(int fd);
-int gem_set_cacheing(int fd, uint32_t handle, int cacheing);
-int gem_get_cacheing(int fd, uint32_t handle);
+int gem_has_caching(int fd);
+int gem_set_caching(int fd, uint32_t handle, int caching);
+uint32_t gem_get_caching(int fd, uint32_t handle);
uint32_t gem_flink(int fd, uint32_t handle);
uint32_t gem_open(int fd, uint32_t name);
void gem_close(int fd, uint32_t handle);
diff --git a/tests/.gitignore b/tests/.gitignore
index 8d0b6e5..6395c73 100644
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -9,7 +9,7 @@ gem_bad_batch
gem_bad_blit
gem_bad_length
gem_basic
-gem_cacheing
+gem_caching
gem_cpu_concurrent_blit
gem_cpu_reloc
gem_cs_prefetch
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 5d0ed3e..8fff22c 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -17,7 +17,7 @@ endif
TESTS_progs_M = \
gem_basic \
- gem_cacheing \
+ gem_caching \
gem_cpu_concurrent_blit \
gem_cs_tlb \
gem_dummy_reloc_loop \
diff --git a/tests/gem_cacheing.c b/tests/gem_cacheing.c
deleted file mode 100644
index 8a169f1..0000000
--- a/tests/gem_cacheing.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Copyright © 2012 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Daniel Vetter <daniel.vetter@xxxxxxxx>
- * Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
- *
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <assert.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
-#include "drmtest.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
-#include "intel_gpu_tools.h"
-
-/*
- * Testcase: snoop consistency when touching partial cachelines
- *
- */
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-
-drm_intel_bo *scratch_bo;
-drm_intel_bo *staging_bo;
-#define BO_SIZE (4*4096)
-uint32_t devid;
-uint64_t mappable_gtt_limit;
-int fd;
-
-static void
-copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
-{
- BEGIN_BATCH(8);
- OUT_BATCH(XY_SRC_COPY_BLT_CMD |
- XY_SRC_COPY_BLT_WRITE_ALPHA |
- XY_SRC_COPY_BLT_WRITE_RGB);
- OUT_BATCH((3 << 24) | /* 32 bits */
- (0xcc << 16) | /* copy ROP */
- 4096);
- OUT_BATCH(0 << 16 | 0);
- OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
- OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(0 << 16 | 0);
- OUT_BATCH(4096);
- OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
- ADVANCE_BATCH();
-
- intel_batchbuffer_flush(batch);
-}
-
-static void
-blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
-{
- uint8_t *gtt_ptr;
- int i;
-
- do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
- gtt_ptr = tmp_bo->virtual;
-
- for (i = 0; i < BO_SIZE; i++)
- gtt_ptr[i] = val;
-
- drm_intel_gem_bo_unmap_gtt(tmp_bo);
-
- if (bo->offset < mappable_gtt_limit &&
- (IS_G33(devid) || intel_gen(devid) >= 4))
- drmtest_trash_aperture();
-
- copy_bo(tmp_bo, bo);
-}
-
-#define MAX_BLT_SIZE 128
-#define ROUNDS 1000
-#define TEST_READ 0x1
-#define TEST_WRITE 0x2
-#define TEST_BOTH (TEST_READ | TEST_WRITE)
-int main(int argc, char **argv)
-{
- unsigned flags = TEST_BOTH;
- int i, j;
- uint8_t *cpu_ptr;
- uint8_t *gtt_ptr;
- bool skipped_all = true;
-
- drmtest_subtest_init(argc, argv);
- drmtest_skip_on_simulation();
-
- srandom(0xdeadbeef);
-
- fd = drm_open_any();
-
- if (!gem_has_cacheing(fd)) {
- printf("no set_caching support detected\n");
- return 77;
- }
-
- devid = intel_get_drm_devid(fd);
- if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
- flags &= ~TEST_READ;
- if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
- /* chipset is completely fubar */
- printf("coherency broken on i965g/gm\n");
- flags = 0;
- }
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
-
- /* overallocate the buffers we're actually using because */
- scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
- gem_set_cacheing(fd, scratch_bo->handle, 1);
-
- staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
-
- drmtest_init_aperture_trashers(bufmgr);
- mappable_gtt_limit = gem_mappable_aperture_size();
-
- if (drmtest_run_subtest("reads") && (flags & TEST_READ)) {
- printf("checking partial reads\n");
- skipped_all = false;
-
- for (i = 0; i < ROUNDS; i++) {
- uint8_t val0 = i;
- int start, len;
-
- blt_bo_fill(staging_bo, scratch_bo, i);
-
- start = random() % BO_SIZE;
- len = random() % (BO_SIZE-start) + 1;
-
- drm_intel_bo_map(scratch_bo, false);
- cpu_ptr = scratch_bo->virtual;
- for (j = 0; j < len; j++) {
- if (cpu_ptr[j] != val0) {
- printf("mismatch at %i, got: %i, expected: %i\n",
- j, cpu_ptr[j], val0);
- exit(1);
- }
- }
- drm_intel_bo_unmap(scratch_bo);
-
- drmtest_progress("partial reads test: ", i, ROUNDS);
- }
- }
-
- if (drmtest_run_subtest("writes") && (flags & TEST_WRITE)) {
- printf("checking partial writes\n");
- skipped_all = false;
-
- for (i = 0; i < ROUNDS; i++) {
- uint8_t val0 = i, val1;
- int start, len;
-
- blt_bo_fill(staging_bo, scratch_bo, val0);
-
- start = random() % BO_SIZE;
- len = random() % (BO_SIZE-start) + 1;
-
- val1 = val0 + 63;
- drm_intel_bo_map(scratch_bo, true);
- cpu_ptr = scratch_bo->virtual;
- memset(cpu_ptr + start, val1, len);
- drm_intel_bo_unmap(scratch_bo);
-
- copy_bo(scratch_bo, staging_bo);
- do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
- gtt_ptr = staging_bo->virtual;
-
- for (j = 0; j < start; j++) {
- if (gtt_ptr[j] != val0) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val0);
- exit(1);
- }
- }
- for (; j < start + len; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
- }
- for (; j < BO_SIZE; j++) {
- if (gtt_ptr[j] != val0) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val0);
- exit(1);
- }
- }
- drm_intel_gem_bo_unmap_gtt(staging_bo);
-
- drmtest_progress("partial writes test: ", i, ROUNDS);
- }
- }
-
- if (drmtest_run_subtest("read-writes") && (flags & TEST_BOTH) == TEST_BOTH) {
- printf("checking partial writes after partial reads\n");
- skipped_all = false;
-
- for (i = 0; i < ROUNDS; i++) {
- uint8_t val0 = i, val1, val2;
- int start, len;
-
- blt_bo_fill(staging_bo, scratch_bo, val0);
-
- /* partial read */
- start = random() % BO_SIZE;
- len = random() % (BO_SIZE-start) + 1;
-
- do_or_die(drm_intel_bo_map(scratch_bo, false));
- cpu_ptr = scratch_bo->virtual;
- for (j = 0; j < len; j++) {
- if (cpu_ptr[j] != val0) {
- printf("mismatch in read at %i, got: %i, expected: %i\n",
- j, cpu_ptr[j], val0);
- exit(1);
- }
- }
- drm_intel_bo_unmap(scratch_bo);
-
- /* Change contents through gtt to make the pread cachelines
- * stale. */
- val1 = i + 17;
- blt_bo_fill(staging_bo, scratch_bo, val1);
-
- /* partial write */
- start = random() % BO_SIZE;
- len = random() % (BO_SIZE-start) + 1;
-
- val2 = i + 63;
- do_or_die(drm_intel_bo_map(scratch_bo, false));
- cpu_ptr = scratch_bo->virtual;
- memset(cpu_ptr + start, val2, len);
-
- copy_bo(scratch_bo, staging_bo);
- do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
- gtt_ptr = staging_bo->virtual;
-
- for (j = 0; j < start; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
- }
- for (; j < start + len; j++) {
- if (gtt_ptr[j] != val2) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val2);
- exit(1);
- }
- }
- for (; j < BO_SIZE; j++) {
- if (gtt_ptr[j] != val1) {
- printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
- j, start, len, gtt_ptr[j], val1);
- exit(1);
- }
- }
- drm_intel_gem_bo_unmap_gtt(staging_bo);
- drm_intel_bo_unmap(scratch_bo);
-
- drmtest_progress("partial read/writes test: ", i, ROUNDS);
- }
- }
-
- drmtest_cleanup_aperture_trashers();
- drm_intel_bufmgr_destroy(bufmgr);
-
- close(fd);
-
- return skipped_all ? 77 : 0;
-}
diff --git a/tests/gem_caching.c b/tests/gem_caching.c
new file mode 100644
index 0000000..d67bbf6
--- /dev/null
+++ b/tests/gem_caching.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ * Daniel Vetter <daniel.vetter@xxxxxxxx>
+ * Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
+ *
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <assert.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include "drm.h"
+#include "i915_drm.h"
+#include "drmtest.h"
+#include "intel_bufmgr.h"
+#include "intel_batchbuffer.h"
+#include "intel_gpu_tools.h"
+
+/*
+ * Testcase: snoop consistency when touching partial cachelines
+ *
+ */
+
+static drm_intel_bufmgr *bufmgr;
+struct intel_batchbuffer *batch;
+
+drm_intel_bo *scratch_bo;
+drm_intel_bo *staging_bo;
+#define BO_SIZE (4*4096)
+uint32_t devid;
+uint64_t mappable_gtt_limit;
+int fd;
+
+static void
+copy_bo(drm_intel_bo *src, drm_intel_bo *dst)
+{
+ BEGIN_BATCH(8);
+ OUT_BATCH(XY_SRC_COPY_BLT_CMD |
+ XY_SRC_COPY_BLT_WRITE_ALPHA |
+ XY_SRC_COPY_BLT_WRITE_RGB);
+ OUT_BATCH((3 << 24) | /* 32 bits */
+ (0xcc << 16) | /* copy ROP */
+ 4096);
+ OUT_BATCH(0 << 16 | 0);
+ OUT_BATCH((BO_SIZE/4096) << 16 | 1024);
+ OUT_RELOC_FENCED(dst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(0 << 16 | 0);
+ OUT_BATCH(4096);
+ OUT_RELOC_FENCED(src, I915_GEM_DOMAIN_RENDER, 0, 0);
+ ADVANCE_BATCH();
+
+ intel_batchbuffer_flush(batch);
+}
+
+static void
+blt_bo_fill(drm_intel_bo *tmp_bo, drm_intel_bo *bo, uint8_t val)
+{
+ uint8_t *gtt_ptr;
+ int i;
+
+ do_or_die(drm_intel_gem_bo_map_gtt(tmp_bo));
+ gtt_ptr = tmp_bo->virtual;
+
+ for (i = 0; i < BO_SIZE; i++)
+ gtt_ptr[i] = val;
+
+ drm_intel_gem_bo_unmap_gtt(tmp_bo);
+
+ if (bo->offset < mappable_gtt_limit &&
+ (IS_G33(devid) || intel_gen(devid) >= 4))
+ drmtest_trash_aperture();
+
+ copy_bo(tmp_bo, bo);
+}
+
+#define MAX_BLT_SIZE 128
+#define ROUNDS 1000
+#define TEST_READ 0x1
+#define TEST_WRITE 0x2
+#define TEST_BOTH (TEST_READ | TEST_WRITE)
+int main(int argc, char **argv)
+{
+ unsigned flags = TEST_BOTH;
+ int i, j;
+ uint8_t *cpu_ptr;
+ uint8_t *gtt_ptr;
+ bool skipped_all = true;
+
+ drmtest_subtest_init(argc, argv);
+ drmtest_skip_on_simulation();
+
+ srandom(0xdeadbeef);
+
+ fd = drm_open_any();
+
+ if (!gem_has_caching(fd)) {
+ printf("no set_caching support detected\n");
+ return 77;
+ }
+
+ devid = intel_get_drm_devid(fd);
+ if (IS_GEN2(devid)) /* chipset only handles cached -> uncached */
+ flags &= ~TEST_READ;
+ if (IS_BROADWATER(devid) || IS_CRESTLINE(devid)) {
+ /* chipset is completely fubar */
+ printf("coherency broken on i965g/gm\n");
+ flags = 0;
+ }
+
+ bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
+ batch = intel_batchbuffer_alloc(bufmgr, devid);
+
+ /* overallocate the buffers we're actually using because */
+ scratch_bo = drm_intel_bo_alloc(bufmgr, "scratch bo", BO_SIZE, 4096);
+ gem_set_caching(fd, scratch_bo->handle, 1);
+
+ staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
+
+ drmtest_init_aperture_trashers(bufmgr);
+ mappable_gtt_limit = gem_mappable_aperture_size();
+
+ if (drmtest_run_subtest("reads") && (flags & TEST_READ)) {
+ printf("checking partial reads\n");
+ skipped_all = false;
+
+ for (i = 0; i < ROUNDS; i++) {
+ uint8_t val0 = i;
+ int start, len;
+
+ blt_bo_fill(staging_bo, scratch_bo, i);
+
+ start = random() % BO_SIZE;
+ len = random() % (BO_SIZE-start) + 1;
+
+ drm_intel_bo_map(scratch_bo, false);
+ cpu_ptr = scratch_bo->virtual;
+ for (j = 0; j < len; j++) {
+ if (cpu_ptr[j] != val0) {
+ printf("mismatch at %i, got: %i, expected: %i\n",
+ j, cpu_ptr[j], val0);
+ exit(1);
+ }
+ }
+ drm_intel_bo_unmap(scratch_bo);
+
+ drmtest_progress("partial reads test: ", i, ROUNDS);
+ }
+ }
+
+ if (drmtest_run_subtest("writes") && (flags & TEST_WRITE)) {
+ printf("checking partial writes\n");
+ skipped_all = false;
+
+ for (i = 0; i < ROUNDS; i++) {
+ uint8_t val0 = i, val1;
+ int start, len;
+
+ blt_bo_fill(staging_bo, scratch_bo, val0);
+
+ start = random() % BO_SIZE;
+ len = random() % (BO_SIZE-start) + 1;
+
+ val1 = val0 + 63;
+ drm_intel_bo_map(scratch_bo, true);
+ cpu_ptr = scratch_bo->virtual;
+ memset(cpu_ptr + start, val1, len);
+ drm_intel_bo_unmap(scratch_bo);
+
+ copy_bo(scratch_bo, staging_bo);
+ do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
+ gtt_ptr = staging_bo->virtual;
+
+ for (j = 0; j < start; j++) {
+ if (gtt_ptr[j] != val0) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val0);
+ exit(1);
+ }
+ }
+ for (; j < start + len; j++) {
+ if (gtt_ptr[j] != val1) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
+ exit(1);
+ }
+ }
+ for (; j < BO_SIZE; j++) {
+ if (gtt_ptr[j] != val0) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val0);
+ exit(1);
+ }
+ }
+ drm_intel_gem_bo_unmap_gtt(staging_bo);
+
+ drmtest_progress("partial writes test: ", i, ROUNDS);
+ }
+ }
+
+ if (drmtest_run_subtest("read-writes") && (flags & TEST_BOTH) == TEST_BOTH) {
+ printf("checking partial writes after partial reads\n");
+ skipped_all = false;
+
+ for (i = 0; i < ROUNDS; i++) {
+ uint8_t val0 = i, val1, val2;
+ int start, len;
+
+ blt_bo_fill(staging_bo, scratch_bo, val0);
+
+ /* partial read */
+ start = random() % BO_SIZE;
+ len = random() % (BO_SIZE-start) + 1;
+
+ do_or_die(drm_intel_bo_map(scratch_bo, false));
+ cpu_ptr = scratch_bo->virtual;
+ for (j = 0; j < len; j++) {
+ if (cpu_ptr[j] != val0) {
+ printf("mismatch in read at %i, got: %i, expected: %i\n",
+ j, cpu_ptr[j], val0);
+ exit(1);
+ }
+ }
+ drm_intel_bo_unmap(scratch_bo);
+
+ /* Change contents through gtt to make the pread cachelines
+ * stale. */
+ val1 = i + 17;
+ blt_bo_fill(staging_bo, scratch_bo, val1);
+
+ /* partial write */
+ start = random() % BO_SIZE;
+ len = random() % (BO_SIZE-start) + 1;
+
+ val2 = i + 63;
+ do_or_die(drm_intel_bo_map(scratch_bo, false));
+ cpu_ptr = scratch_bo->virtual;
+ memset(cpu_ptr + start, val2, len);
+
+ copy_bo(scratch_bo, staging_bo);
+ do_or_die(drm_intel_gem_bo_map_gtt(staging_bo));
+ gtt_ptr = staging_bo->virtual;
+
+ for (j = 0; j < start; j++) {
+ if (gtt_ptr[j] != val1) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
+ exit(1);
+ }
+ }
+ for (; j < start + len; j++) {
+ if (gtt_ptr[j] != val2) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val2);
+ exit(1);
+ }
+ }
+ for (; j < BO_SIZE; j++) {
+ if (gtt_ptr[j] != val1) {
+ printf("mismatch at %i, partial=[%d+%d] got: %i, expected: %i\n",
+ j, start, len, gtt_ptr[j], val1);
+ exit(1);
+ }
+ }
+ drm_intel_gem_bo_unmap_gtt(staging_bo);
+ drm_intel_bo_unmap(scratch_bo);
+
+ drmtest_progress("partial read/writes test: ", i, ROUNDS);
+ }
+ }
+
+ drmtest_cleanup_aperture_trashers();
+ drm_intel_bufmgr_destroy(bufmgr);
+
+ close(fd);
+
+ return skipped_all ? 77 : 0;
+}
diff --git a/tests/gem_partial_pwrite_pread.c b/tests/gem_partial_pwrite_pread.c
index ee176b1..0330216 100644
--- a/tests/gem_partial_pwrite_pread.c
+++ b/tests/gem_partial_pwrite_pread.c
@@ -258,7 +258,7 @@ static void do_tests(int cache_level, const char *suffix)
char name[80];
if (cache_level != -1) {
- switch (gem_set_cacheing(fd, scratch_bo->handle, cache_level)) {
+ switch (gem_set_caching(fd, scratch_bo->handle, cache_level)) {
case 0: break;
case -EINVAL:
case -ENOTTY:
diff --git a/tests/gem_pread.c b/tests/gem_pread.c
index 7037221..7c2f18f 100644
--- a/tests/gem_pread.c
+++ b/tests/gem_pread.c
@@ -120,7 +120,7 @@ int main(int argc, char **argv)
}
for (c = cache; c->level != -1; c++) {
- if (gem_set_cacheing(fd, dst, c->level))
+ if (gem_set_caching(fd, dst, c->level))
continue;
for (count = 1; count <= 1<<17; count <<= 1) {
diff --git a/tests/gem_pread_after_blit.c b/tests/gem_pread_after_blit.c
index dce8241..55caa98 100644
--- a/tests/gem_pread_after_blit.c
+++ b/tests/gem_pread_after_blit.c
@@ -131,8 +131,8 @@ static void do_test(int fd, int cache_level,
int loop)
{
if (cache_level != -1) {
- if (gem_set_cacheing(fd, tmp[0]->handle, cache_level) ||
- gem_set_cacheing(fd, tmp[1]->handle, cache_level))
+ if (gem_set_caching(fd, tmp[0]->handle, cache_level) ||
+ gem_set_caching(fd, tmp[1]->handle, cache_level))
return;
}
diff --git a/tests/gem_pwrite.c b/tests/gem_pwrite.c
index 447a200..f939b9f 100644
--- a/tests/gem_pwrite.c
+++ b/tests/gem_pwrite.c
@@ -127,7 +127,7 @@ int main(int argc, char **argv)
}
for (c = cache; c->level != -1; c++) {
- if (gem_set_cacheing(fd, dst, c->level))
+ if (gem_set_caching(fd, dst, c->level))
continue;
for (count = 1; count <= 1<<17; count <<= 1) {
diff --git a/tests/gem_pwrite_pread.c b/tests/gem_pwrite_pread.c
index 1f9187f..65427c3 100644
--- a/tests/gem_pwrite_pread.c
+++ b/tests/gem_pwrite_pread.c
@@ -398,8 +398,8 @@ int main(int argc, char **argv)
src = gem_create(fd, object_size);
tmp = malloc(object_size);
- if (gem_set_cacheing(fd, src, 0) == 0 &&
- gem_set_cacheing(fd, dst, 0) == 0) {
+ if (gem_set_caching(fd, src, 0) == 0 &&
+ gem_set_caching(fd, dst, 0) == 0) {
if (drmtest_run_subtest("uncached-copy-correctness"))
test_copy(fd, src, dst, tmp, object_size);
if (drmtest_run_subtest("uncached-copy-performance")) {
@@ -435,8 +435,8 @@ int main(int argc, char **argv)
}
}
- if (gem_set_cacheing(fd, src, 1) == 0 &&
- gem_set_cacheing(fd, dst, 1) == 0) {
+ if (gem_set_caching(fd, src, 1) == 0 &&
+ gem_set_caching(fd, dst, 1) == 0) {
if (drmtest_run_subtest("snooped-copy-correctness"))
test_copy(fd, src, dst, tmp, object_size);
if (drmtest_run_subtest("snooped-copy-performance")) {
@@ -472,8 +472,8 @@ int main(int argc, char **argv)
}
}
- if (gem_set_cacheing(fd, src, 2) == 0 &&
- gem_set_cacheing(fd, dst, 2) == 0) {
+ if (gem_set_caching(fd, src, 2) == 0 &&
+ gem_set_caching(fd, dst, 2) == 0) {
if (drmtest_run_subtest("display-copy-correctness"))
test_copy(fd, src, dst, tmp, object_size);
if (drmtest_run_subtest("display-copy-performance")) {
--
1.8.3.2
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